Output buffer synchronizing circuit having selectively variable

Details Output buffer synchronizing circuit having selectively variable Output buffer synchronizing circuit having selectively variable

1977-01-24

1978-03-14

Thomas, James D.

Boots, shoes, and leggings

G06F 104, G06F 300

Patent

active

040794563

ABSTRACT:
Output buffer synchronizing circuit having selectively variable delay means to compensate for different output delays of a processor when the latter operates in different modes. A buffer clock is not only synchronized with the processor clock but also switched in frequency only when in proper phase therewith by delaying a reference signal by kT.sub.R /N, where N is the ratio of the reference period to the processor clock period, T.sub.R is the reference period, and k is a selectable integer such that 0 .ltoreq. k - N.ltoreq.1.

REFERENCES:
patent: 3516074 (1970-06-01), Enomoto
patent: 4021784 (1977-05-01), Kimlinger

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