Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
1998-09-21
2001-05-08
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S534000
Reexamination Certificate
active
06229380
ABSTRACT:
The present invention concerns an output buffer circuit for outputting digital signals and a method of operating an output buffer circuit.
A variety of concepts for digital logic circuits and digital signalling between circuits is presently known. Early concepts are DTL (Diode-Transistor Logic), TTL (Transistor-Transistor Logic) and ECL (Emitter Coupled Logic), which concepts are used with digital logic circuits as well as for digital signalling between circuits or circuit boards.
Concepts designed for transmission of digital data with a high data rate preferably employ a differential transmission and reception of digital data, using a pair of signalling wires. DPECL (Differential Positive Emitter Coupled Logic), LVDS (Low Voltage Differential Signalling) and GLVDS (Grounded Low Voltage Differential Signalling) are examples of signalling concepts which use differential signalling. Differential signalling enables keeping the differential voltage across the pair of signalling wires low as due to the differential concept spurious voltage drops across a ground line connecting the transmitter with the receiver will not adversely affect the quality of data transmission. Low differential signalling voltages in turn keep the power transmitted over low impedance transmission lines within reasonable limits.
With the ever increasing complexity of digital circuitry along with a rapid increase of the scale of integration the power efficiency of a specific circuit design becomes more and more important. Given a specified limit for the power dissipation density (power dissipation per unit area), the maximum allowable power dissipation of each circuit component is the lower the higher the integration density. Vice versa, the larger the power dissipation of a particular component, the larger the area occupied by this component on a semiconductor chip.
Power dissipation is a particular problem when designing low impedance output buffer stages operating in a system environment with supply voltages higher than the differential voltage amplitude across the output terminals of the output buffer circuit. In this case, comparatively high currents output by the buffer circuit result in a large amount of power dissipation in the output stages of the buffer.
All the above-mentioned differential signalling concepts operate at fixed nominal voltages related to ground. Each wire operates at two voltage levels referred to as low voltage level and high voltage level, respectively. As an example, DPECL operates with a low voltage level of 3.3 volt and a high voltage level of 4.1 volt. LVDS on the other hand has a low voltage level of 1.0 volt and a high voltage level of 1.4 volt. GLVDS operates with signal levels close to ground, for instance 0 volt and 0.2 volt or approximately symmetrical with respect to ground with an amplitude of about 0.2 volt.
When considering all differential signalling concepts presently available, signalling voltages span from slightly below 0 volt up to more than 4 volt. As a consequence, it is not possible to connect an output buffer circuit conforming to one differential signalling concept with an input conforming to a different signalling concept. Accordingly, a complex circuit design must either stick to a specific signalling concept or must include means for translating between the different signalling levels. The first alternative has the drawback that future developments lack flexibility while the latter alternative requires additional space and power not related to the core functions of the system.
The present invention aims at solving the above-mentioned problems. It is the object of the invention, to provide a power efficient output buffer circuit and a method of operating the same, suitable for driving low impedance transmission lines at high data rates and enabling a space efficient implementation on a semiconductor chip.
It is a further object of the present invention, to provide an output buffer circuit suitable for cooperation with a variety of differential signalling concepts at different voltage levels without sacrificing power efficiency or space on the chip surface.
An output buffer circuit for outputting digital signals according to the present invention comprises an amplifier section for driving a load, e.g. a symmetrical low impedance transmission line or two asymmetric low impedance transmission lines, and moreover comprises a power supply section for supplying power to the amplifier section. The power supply section comprises a pair of input terminals for connection with a power source and a pair of output terminal for connection with said amplifier section; reactance means for temporarily storing energy; and switching means adapted to provide a charging phase in which energy from said power source is charged into said reactance means and a discharging phase in which at least a part of the energy stored in said reactance means is discharged into said output terminals.
A method of operating an output buffer circuit having an amplifier section and a power supply section including input terminals, reactance means for temporarily storing energy and output terminals connected to said amplifier section, according to the present invention comprises the steps connecting the input terminals to a voltage source; connecting said reactance means to said input terminals for charging energy into said reactance means; and connecting said reactance means to said output terminals for discharging at least a part of said energy into said amplifier section.
According to the present invention, a reactance means, for example an inductor or a capacitor, receives energy from a voltage source during a charging phase and forwards this energy to the amplifier section during a discharge phase. By means of appropriately setting the duration of the charging phase and the duration of the discharging phase, it is possible to provide the amplifier section with a supply voltage suitable for power efficient operation without dissipating large amounts of power and thus without generating large amounts of heat. This is possible because suitably setting the duration of the charging phase in relation to the duration of the discharging phase enables transferring just as much power to the amplifier section as is needed for the proper operation, without dissipating excessive power in the power supply section or in the amplifier section.
According to a specific embodiment of the present invention the switching means adapted to provide the charging phase and the discharging phase, respectively, comprises a first semiconductor switch for performing the charging phase, connected between one input terminal of the pair of input terminals and a first terminal of said reactance means. Moreover, said switching means comprises a second semiconductor switch for performing the discharging phase, connected between said first terminal of said reactance means and one output terminal of said pair of output terminals. The second terminal of said reactance means is connected to the other output terminal of said pair of output terminals. In this way, during the charging phase the first switch establishes a loop including the power source connected to the input terminals of the power supply section and the reactance means. This loop may also include the load, i.e. the amplifier section. During the discharging phase the second switch establishes a loop including the reactance means and the load. This embodiment is advantageous for LVDS (low voltage differential signalling) applications, GLVDS (grounded low voltage differential signalling) and DPECL (differential positive emitter coupled logic) applications. According to another specific embodiment of the present invention, the switching means adapted to provide the charging phase and the discharging phase, respectively, provides for disconnection of both input terminals of the power supply section from both output terminals of the power supply section during both the charging phase and the discharging phase. In this way the voltage across the output terminals is floatin
Burns Doane Swecker & Mathis L.L.P.
Cunningham Terry D.
Telefonaktiebolaget LM Ericsson (publ)
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