Output buffer semiconductor and method for controlling current f

Details Output buffer semiconductor and method for controlling current f Output buffer semiconductor and method for controlling current f

1988-11-22

1991-01-15

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307448, 307542, 307546, 307572, 36518905, H03K 1716

Patent

active

049856448

ABSTRACT:
An output buffer circuit comprises a NAND circuit and a NOR circuit each receiving an output a of a signal source and an output b of an output control circuit and an output driving circuit formed by a p channel MOS transistor and an n channel MOS transistor receiving outputs of the NAND circuit and the NOR circuit. Large output capacitance is connected to an output of the output driving circuit. The n channel MOS transistor is connected between the output of the NOR circuit and a ground potential, and has its gate receiving the output of the output driving circuit. When the output of the output driving circuit is at an "H" level, the rise of the output of the NOR circuit is controlled, so that the output of the output driving circuit is first changed to the "L" level slowly. Therefore, discharge current from the output capacitance rises slowly. However, since transconductance of the n channel MOS transistor in the output driving circuit is set large, the output of the output driving circuit falls rapidly from halfway.

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patent: 4829199 (1989-05-01), Prater
patent: 4837458 (1989-06-01), Kawahata et al.
patent: 4845681 (1989-07-01), Vu et al.

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