Output buffer or voltage hold for analog of multilevel processin

Details Output buffer or voltage hold for analog of multilevel processin Output buffer or voltage hold for analog of multilevel processin

1998-07-02

2000-10-03

Cunningham, Terry D.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

327436, 327437, H03K 1900

Patent

active

061278572

ABSTRACT:
In order to prevent an output offset voltage from occurring because of a relative difference of threshold voltage Vth between NMOS and PMOS in transmission of dc voltage, a semiconductor integrated circuit is constructed in a circuit configuration comprising a first depletion-mode N-channel MOS transistor and a first depletion-mode P-channel MOS transistor, a gate of each transistor being connected to an input terminal and a source of each transistor being connected to an output terminal, a second depletion-mode N-channel MOS transistor having W/L equal to that of the first depletion-mode P-channel MOS transistor, a drain of the transistor being connected to the output terminal and a gate and a source of the transistor being connected both to a lower-voltage-side power supply, and a second depletion-mode P-channel MOS transistor having W/L equal to that of the first depletion-mode P-channel MOS transistor, a drain of the transistor being connected to the output terminal and a gate and a source of the transistor being connected both to a higher-voltage-side power supply.

REFERENCES:
patent: 4476448 (1984-10-01), Saari
patent: 4656611 (1987-04-01), Suyama
patent: 4712023 (1987-12-01), Otsuki et al.
patent: 4760284 (1988-07-01), Taylor
patent: 4939390 (1990-07-01), Coe
patent: 5459428 (1995-10-01), Kim et al.
patent: 5541444 (1996-07-01), Ohmi et al.
patent: 5744994 (1998-04-01), Williams
patent: 5834962 (1998-11-01), Okamoto
patent: 5835045 (1998-11-01), Ogawa et al.

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