Output buffer having sequentially-switched output

Details Output buffer having sequentially-switched output Output buffer having sequentially-switched output

1986-12-08

1988-12-06

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307246, 307270, 307296R, 307548, H03K 1704, H03K 1712, H03K 17284, H03K 17687

Patent

active

047897961

ABSTRACT:
An integrated semiconductor circuit includes an output stage and a control circuit. The output stage comprises several (e.g. four) pull-down output transistors, which are sequentially switched on for pulling down the output node, whereby four small current steps are made instead of one high current step. As a result the package inductance generated power supply line noise will be substantially reduced (by at least a factor four). The same technique can be used for limiting the supply line noise due to the charge current for charging the output node via pull-up transistors.

REFERENCES:
patent: 3248657 (1966-04-01), Turecki
patent: 3654491 (1972-04-01), Earp
patent: 3911289 (1975-10-01), Takemoto
patent: 4359654 (1982-11-01), Buckendorf et al.
patent: 4472643 (1984-09-01), Furuyama
patent: 4487457 (1984-12-01), Janutka
patent: 4567379 (1986-01-01), Corey et al.
patent: 4682047 (1987-07-01), von Sichart
"CMOS Inverter Optimization", IBM Tech. Discl. Bull., vol. 28, No. 2, pp. 790-791, Jul. 1985.

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