Output buffer having distributed stages to reduce switching nois

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307451, 307594, 307601, 307263, H03K 1716, H03K 19003, H03K 513, H03K 5159

Patent

active

049926764

ABSTRACT:
An output buffer integrated circuit, including an output signal, is provided having an improved Vdd and Vss noise characteristics. The output buffer comprise a plurality of pull-up stages and pull-down stages functioning as complementary pairs. The pull-up stage pulls the output signal to the Vdd potential, and the pull-down stages pulls the output to the Vss potential. Each stage provides a pulling signal to turn on a pulling transistor in response to the pulling signal of the previous stage. The first pulling stage provides the pulling signal in response to the input signal. Each stage sequentially pulls the output signal within a substantially constant time. The constant time delay within each stage is provided by sizing the width of the active elements on the integrated circuit. The pulling stages turn off the pulling transistors instantaneously in response to the invert of the input signal.

REFERENCES:
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patent: 4612466 (1986-09-01), Stewart
patent: 4725747 (1988-02-01), Stein
patent: 4785203 (1988-11-01), Nakamura
patent: 4789793 (1988-12-01), Ehni
patent: 4806794 (1989-02-01), Walters, Jr.
patent: 4882505 (1989-11-01), Furman
patent: 4885485 (1989-12-01), Leake et al.

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