Output buffer for semiconductor integrated circuit

Details Output buffer for semiconductor integrated circuit Output buffer for semiconductor integrated circuit

1991-10-16

1993-06-01

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, H03K 19092, H03K 19094

Patent

active

052163008

ABSTRACT:
An output buffer of a semiconductor integrated circuit, including a P channel MOS transistor connected between first power source and an output terminal and a first N channel MOS transistor connected between a second power source and the output terminal, the first P and N channel MOS transistors being complementarily brought into a conductive state depending upon the level of an input signal given to the gates thereof for driving an output load including a signal transmission line connected with the output terminal is characterized in that each of said P and N channel MOS transistors has an output resistance equal to the characteristic impedance of the signal transmission line and in that said output buffer further includes an auxiliary control unit comprising a second N channel MOS transistor having an output resistance equal to the characteristic impedance of the signal transmission line connected in parallel with said first N channel MOS transistor between the second power source and the output terminal, and a pulse generating circuit and a drive circuit for determining the conduction period of time of the second N channel MOS transistor, which is connected with the gate of the second N channel MOS transistor.

REFERENCES:
patent: 4785201 (1988-11-01), Martinez
patent: 4785203 (1988-11-01), Nakamura
patent: 4825101 (1989-04-01), Walters, Jr.
patent: 4829199 (1989-05-01), Prater
patent: 4855623 (1989-08-01), Flaherty
patent: 4961010 (1990-10-01), Davis
patent: 5003205 (1991-03-01), Kohda et al.
patent: 5008568 (1991-04-01), Leung et al.
patent: 5089722 (1992-02-01), Amedeo

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