Output buffer control circuit of memory device

Details Output buffer control circuit of memory device Output buffer control circuit of memory device

1988-05-24

1989-08-15

Popek, Joseph A.

Static information storage and retrieval

Addressing

Sync/clocking

365190, G11C 800

Patent

active

048581976

ABSTRACT:
In an output buffer control circuit of a memory, the set/reset state of a flip-flop is controlled by an address transition detection output and a read detection output supplied when completion of data read from a memory cell is detected, and the active/inactive state of an output buffer for outputting the readout data from the memory cell is controlled by an output from the flip-flop. According to this arrangement, when an address input transits and the address transition detection output is enabled, the output buffer is inactivated. When data is read out from the memory cell and the read detection output is enabled after the address input transits, the output buffer can be activated.

REFERENCES:
patent: 4573147 (1986-02-01), Aoyama et al.
patent: 4616342 (1986-10-01), Miyamoto
patent: 4744063 (1988-05-01), Ohtani et al.
T. Wada et al., "A 34ns 1Mb CMOS SRAM Using Triple Poly," IEEE International Solid-State Circuits Conference, Digest of Technical Papers, Session 19.7, pp. 262-263, Feb., 1987.
M. Isobe et al., "A 46ns 256K CMOS RAM," IEEE International Solid-State Circuits Conference, pp. 214-215, Feb., 1984.

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