Output buffer circuit with control circuit for changing...

Details Output buffer circuit with control circuit for changing... Output buffer circuit with control circuit for changing...

2006-09-08

2008-08-05

Richards, N. Drew (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S563000

Reexamination Certificate

active

07408387

ABSTRACT:
Disclosed is an output buffer circuit including a first differential transistor pair for differentially receiving a data signal from a differential input pair; and a second differential transistor pair for differentially receiving an emphasis data signal from another differential input pair; a pair of output resistor circuits via which the drains of first and second differential transistor pairs are connected to a power supply, said output resistor circuits each including a transistor; and a logic circuit adapted for receiving the data signal and the emphasis signal and for supplying a control signal which is of first and second values at the time of preemphasis and at other times to the transistors of the output resistor circuit, wherein the output resistance is relatively made larger at the time of emphasis, while being relatively smaller at the time of deemphasis.

REFERENCES:
patent: 6281715 (2001-08-01), DeClue et al.
patent: 6288581 (2001-09-01), Wong
patent: 6703894 (2004-03-01), Stockstad et al.
patent: 6853220 (2005-02-01), De Laurentiis et al.
patent: 6897685 (2005-05-01), Sato
patent: 6956407 (2005-10-01), Baig et al.
patent: 7164299 (2007-01-01), Nedachi
patent: 7183813 (2007-02-01), Kasanyal et al.
patent: 7256626 (2007-08-01), Nguyen et al.
patent: 2004-015621 (2004-01-01), None
patent: 2004-088693 (2004-03-01), None

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