Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Slope control of leading or trailing edge of rectangular or...
Reexamination Certificate
1999-04-15
2001-05-01
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Slope control of leading or trailing edge of rectangular or...
C327S108000, C327S112000, C327S437000
Reexamination Certificate
active
06225844
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an output buffer circuit. More particularly, the present invention relates to a slew rate buffer type of an output buffer circuit having a function of controlling a slew rate of an output signal.
2. Description of the Related Art
In general, an output buffer circuit having this type of slew rate control function is used for an output in a signal system, in which a speed is slow, such as a reset signal, a stop signal, a standby signal. The slew rate control function enables the stable operation in which a load circuit receiving the output signal does not suffer from the influence, such as high harmonic noise, ringing.
A conventional type of output buffer circuit is, for example, disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 8-56147) ('147), Japanese Laid Open Patent Application (JP-A-Heisei 4-172012) ('012), Japanese Laid Open Patent Application (JP-A-Heisei 5-191259) ('259), Japanese Laid Open Patent Application (JP-A-Heisei 1-171317) ('317), Japanese Laid Open Patent Application (JP-A-Heisei 5-347545) ('545), Japanese Laid Open Patent Application (JP-A-Heisei 5-114852) ('852) and Japanese Laid Open Patent Application (JP-A-Heisei 6-252723) ('723).
The conventional first output buffer circuit disclosed in the '147 publication will be described below with reference to FIG.
1
. The conventional first output buffer circuit is provided with inverters IV
1
, IV
2
, a P-channel MOS transistor P
1
, an N-channel MOS transistor N
1
, a bias circuit
103
, a P-channel MOS transistor P
2
, an N-channel MOS transistor N
2
, a bias circuit
104
, a slew rate control circuit
101
, a slew rate control circuit
102
, an output buffer
2
, a schmitt trigger ST
1
and a schmitt trigger ST
2
.
The inverters IV
1
, IV
2
are connected in series, and then receive an input signal IN, and further output signals IB, IBB, respectively. In the P-channel MOS transistor P
1
, a source thereof is connected to a power supply VDD, and a gate thereof is connected to the output of the inverter IV
1
, respectively. In the N-channel MOS transistor N
1
, a source thereof is connected to a ground G, and a gate thereof is connected to an output of the schmitt trigger ST
1
, respectively. The bias circuit
103
is inserted between respective drains of the transistors P
1
, N
1
, and then outputs bias voltages B
1
, B
1
B.
In the P-channel MOS transistor P
2
, a source thereof is connected to the power supply VDD, and a gate thereof is connected to an output of the schmitt trigger ST
2
, respectively. In the N-channel MOS transistor N
2
, a source thereof is connected to the ground G, and a gate thereof is connected to the output of the inverter IV
1
, respectively. The bias circuit
104
is inserted between respective drains of the transistors P
2
, N
2
, and then outputs bias voltages B
2
, B
2
B.
The slew rate control circuit
101
receives the output signal IBB of the inverter IV
2
and the bias voltages B
1
, B
1
B, and then outputs a slew rate control signal T
1
. The slew rate control circuit
102
receives the output signal IBB of the inverter IV
2
and the bias voltages B
2
, B
2
B, and then outputs a slew rate control signal T
2
. An output buffer
2
outputs an output signal O to an output terminal TO, in response to the supply of the signals T
1
, T
2
. The schmitt trigger ST
1
sends an output signal S
1
to the gate of the transistor N
1
, in response to the supply of the signal T
1
. The schmitt trigger ST
2
sends an output signal S
2
to the gate of the transistor P
2
, in response to the supply of the signal T
2
.
The output buffer
2
is provided with a P-channel MOS transistor P
21
that is a pull-up transistor and an N-channel MOS transistor N
21
that is a pull-down transistor. In the P-channel MOS transistor P
21
, a source thereof is connected to the power supply VDD, and a drain thereof is connected to the output terminal TO, respectively, and the gate receives the signal T
1
. In the N-channel MOS transistor N
21
, a drain thereof is connected to the drain of the transistor P
21
, and a source thereof is connected to the ground G, respectively, and the gate receives the signal T
2
.
The slew rate control circuit
101
is provided with a P-channel MOS transistor P
101
, an N-channel MOS transistor N
101
, a P-channel MOS transistor P
102
and a capacitor C
101
.
In the P-channel MOS transistor P
101
, a source thereof is connected to the power supply VDD, and then a gate thereof receives the signal B
1
, and a drain thereof outputs the signal T
1
. In the N-channel MOS transistor N
101
, a drain thereof is connected to the drain of the transistor P
101
, and a source thereof is connected to the ground G, respectively, and then a gate thereof receives the signal B
1
B. In the P-channel MOS transistor P
102
, a gate thereof is connected to the output of the inverter IV
2
, a source thereof is connected to the power supply VDD, and a drain thereof is connected to the drain of the transistor P
101
, respectively. The capacitor C
101
is connected between the drain of the transistor P
102
and the ground G, and then generates a gate capacitance of the transistor P
21
in the output buffer circuit
2
.
The slew rate control circuit
102
is provided with a P-channel MOS transistor P
103
, an N-channel MOS transistor N
102
, an N-channel MOS transistor N
103
and a capacitor C
102
.
In the P-channel MOS transistor P
103
, a source thereof is connected to the power supply VDD, and then a gate thereof receives the signal B
2
, and a drain thereof outputs the signal T
2
.
In the N-channel MOS transistor N
102
, a drain thereof is connected to the drain of the transistor P
103
, and a source thereof is connected to the ground G, respectively, and then a gate thereof receives the signal B
2
B. In the N-channel MOS transistor N
103
, a gate thereof is connected to the output of the inverter IV
2
, a source thereof is connected to the ground G, and a drain thereof is connected to the drain of the transistor P
103
, respectively. The capacitor C
102
is connected between the drain of the transistor N
102
and the ground G, and then generates a gate capacitance of the transistor N
21
in the output buffer circuit
2
.
The operations of the conventional first output buffer circuit will be described below with reference to FIG.
2
.
At first, suppose that the operations start from a stable state in which the input signal IN and the output signal O are in an L level, that is ‘0’. At this time, the transistor P
21
of the output buffer
2
is in an off-state, and the transistor N
21
is in an on-state. This indicates that the signals T
1
, T
2
are ‘1’.
In accordance with an H level of the signal T
2
, the input to the schmitt trigger ST
2
is also ‘1’, and then the output signal S
2
of the schmitt trigger ST
2
is ‘1’, and further the transistor P
2
is in the off-state.
Moreover, since the input signal IN is ‘0’, the signal IB is ‘1’, and then the signal IBB is ‘0’, and thereby the transistor N
103
is in the off-state, and the transistor N
2
is in the on-state. Accordingly, the bias circuit
104
becomes inactive, and the bias voltages B
2
, B
2
B are equal to a potential of the ground G. Thus, the transistor N
102
is in the off-state, and the transistor P
103
becomes in a linear area and functions as a resistor. Hence, the signal T
2
corresponds to a potential of a condition that it is connected through a resistive clamp to the power supply VDD.
Similarly, if the signal T
1
is ‘1’, the input to the schmitt trigger ST
1
is ‘1’, and then the output signal S
1
of the schmitt trigger ST
1
is ‘1’, and further the transistor N
1
is in the on-state. Moreover, since the input signal IN is ‘0’, the transistor P
1
is in the off-state, and also the transistor P
102
is in the on-state. The bias circuit
103
is inactive, and the bias voltages B
1
, B
1
B are equal to the potential of the ground G. Accordingly, the transistor N
101
is in the off-state, and the
McGinn & Gibb PLLC
NEC Corporation
Wells Kenneth B.
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