Output buffer circuit of semiconductor integrated circuit

Details Output buffer circuit of semiconductor integrated circuit Output buffer circuit of semiconductor integrated circuit

2001-10-30

2002-10-29

Nuton, My-Trang (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C326S083000

Reexamination Certificate

active

06472911

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to technology for decreasing the malfunctions of an output buffer circuit provided to a semiconductor integrated circuit, and may be employed in an output buffer circuit for outputting logic signals.
2. Description of Related Art
An output buffer circuit is provided to a semiconductor integrated circuit. A general output buffer circuit comprises a pair of PMOS transistors and nMOS transistors. With a general output buffer circuit, the pMOS transistor is connected between a signal output terminal of the integrated circuit and a high-voltage generating line, and the nMOS transistor is connected between this signal output terminal and a low-voltage generating line (usually a ground line) . When a logic signal is supplied to this pair of transistors, one of the transistors will be turned on and the other turned off. The output logic signal of the output buffer circuit is, for example, a high level when the pMOS transistor is turned on and a low level when the nMOS transistor is turned on.
The voltage value of the logic signal output from the output buffer circuit is, for example, several milliampere, which is an extremely large value. Thus, used as the transistor for structuring the output buffer circuit is a transistor with a large dimension; that is, a transistor having a large gate width and gate length.
With the output buffer circuit, switching noise is generated when the logic value of the output signal is switched. The switching noise vibrates the output potential of the output buffer circuit from the reversal of the logic value for a certain amount of time.
When numerous output buffer circuits are connected to the same power source and the same logical change is simultaneously implemented, the current flowing in the power supply line becomes extremely large. And, when the current flowing in the power supply line is extremely large, the switching noise of the output signal becomes large. An extremely large switching noise may cause malfunctions in the output buffer circuit.
When the power source current is small, the possibility of a malfunction occurring due to the switching noise is small. When lowering the power source current, however, the drive performance of the output circuit will decrease.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an output buffer circuit of a semiconductor integrated circuit that will not malfunction easily.
Therefore, the output buffer circuit of a semiconductor integrated circuit according to the present invention comprises: a main driver having a first transistor for increasing and decreasing the current flowing between a signal output terminal and a first power supply line inversely depending on a first control potential, and a second transistor for increasing and decreasing the current flowing between the signal output terminal and a second power supply line depending on a second control potential; and a predriver for generating the first control potential and the second control potential by employing an input logic signal, and reducing the increase speed of the current of the first transistor or the second transistor by prolonging the fall time of the first control potential or rise time of the second control potential.
With the output buffer circuit according to the present invention, it is possible to decrease the peak value of switching noise by reducing the current increase speed when the first transistor or the second transistor is switched on. Thus, malfunctions in the output buffer circuit of the present invention do not occur easily.


REFERENCES:
patent: 5949259 (1999-09-01), Garcia
patent: 6060938 (2000-05-01), Morrill
patent: 6236248 (2001-05-01), Koga
patent: 6285236 (2001-09-01), Stephens
patent: 6304120 (2001-10-01), Taito
patent: 6320432 (2001-11-01), Nagao
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patent: 10-163826 (1998-06-01), None

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