Output buffer circuit of semiconductor integrated circuit

Details Output buffer circuit of semiconductor integrated circuit Output buffer circuit of semiconductor integrated circuit

1989-07-11

1991-01-15

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307263, 3072964, 307592, 307594, 307603, H03K 19017, H03K 512, H03K 5159

Patent

active

049856464

ABSTRACT:
An output buffer produces an output data at an output terminal. A first MOS transistor charges the output terminal toward a first supply potential when turned on. The source and drain of the first MOS transistor are connected between the output terminal and a first supply potential terminal. A second MOS transistor discharges the output terminal toward a second supply potential when turned on. The source and drain of the second MOS transistor are connected between the output terminal and a second supply potential terminal. A resistive element charges the gate of the second MOS transistor toward the first supply potential when turned on. The resistive element is connected between the first supply potential terminal and the gate of the second MOS transistor. The resistance value of the resistive element has nearly a constant value.

REFERENCES:
patent: 4758743 (1988-07-01), Dehganpour et al.
patent: 4818901 (1989-04-01), Young et al.
patent: 4827159 (1989-05-01), Naganuma
IBM Technical Disclosure Bulletin Published May 9, 1985.
Wang et al., "A21-ns 32Kx8 CMOS Static RAM with a Selectively Pumped P-Well Array," IEEE Journal of Solid-State Circuits, vol. SC-22, No. 5, Oct. 1987.

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