Output buffer circuit having output bouncing controlled circuits

Details Output buffer circuit having output bouncing controlled circuits Output buffer circuit having output bouncing controlled circuits

1992-01-17

1994-06-21

Hudspeth, David R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307446, 307448, H03K 19092, H03K 1716

Patent

active

053230701

ABSTRACT:
A first output buffer having a large current driving capability and a second output buffer having a small current driving capability are connected in parallel between an input terminal and an external lead. The first and second output buffers each includes two CMOS inverters connected in series between the input terminal and the external lead. The P-channel and N-channel MOSFETs of the two CMOS inverters in the second output buffer have gate widths smaller than each of the P-channel and N-channel MOSFETs, respectively, of the two CMOS inverters in the first output buffer. Also disclosed is an output buffer having P-channel and N-channel MOSFETs arranged as a CMOS inverter, but with a base of a first bipolar transistor connected to a source of the N-channel MOSFET. An emitter of the first bipolar transistor is connected to ground and its collector is connected to an output of the output buffer. A base of a second bipolar transistor is connected to an output of the CMOS inverter and its emitter is connected to the output of the output buffer. An input of the output buffer is supplied to an input of the CMOS inverter. Another transistor is connected between the output of the output buffer and ground and is responsive to the input of the output buffer.

REFERENCES:
patent: 4779013 (1988-10-01), Tanaka
patent: 4855623 (1989-08-01), Flaherty
patent: 4890016 (1989-12-01), Tanaka et al.
patent: 5066875 (1991-11-01), Ueno et al.
patent: 5107142 (1992-04-01), Bhamidipaty
patent: 5122690 (1992-06-01), Bianchi
Masahiro Kimura et al., Technical Research Report of the Institute of Electronics, Information and Communication Engineers, Jul 19, 1991, pp. 69-73 "A Low Noise, High Drivability Output Buffer for BiCMOS Standard Cell Libraries".
Kam Leung, "Controlled Slew Rate Output Buffer", IEEE 1988 Custom Integrated Circuits Conference, 1988, pp. 5.5.1-5.5.4.
Ichiro Tomioka et al., "Current Control Buffer for Multi Switching CMOS SOG", IEEE 1990 Custom Integrated Circuits Conference, pp. 11.7.1-11.7.4.

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