Output buffer circuit having changeable output impedance

Details Output buffer circuit having changeable output impedance Output buffer circuit having changeable output impedance

1999-11-23

2001-10-09

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S540000, C326S030000

Reexamination Certificate

active

06300821

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to an output buffer circuit, and more particularly, to an output buffer whose output impedance can be changed.
As structure for a large scale integrations (LSls) becomes smaller and smaller, the quality of the LSI may become uneven. This creates a problem because there is a difference in impedance between a one output buffer and another output buffer even in the same LSI. For example, the difference in the impedance between output buffers becomes about +/−30 percent. The difference in the impedance between output buffers produces signal reflection, which deteriorates the performance of the LSI.
SUMMARY OF THE INVENTION
An object of the invention is to provide an output buffer circuit whose output impedance can be changed.
According to one aspect of the present invention, an output buffer circuit is provided which includes: a buffer circuit; a first element which counts to a value based on a clock signal and outputs the counted value; a second element which controls the first element based on an output from the buffer circuit; and a third element which inputs the counted value and controls the impedance of the buffer circuit based on the counted value.
According to another aspect of the present invention, an output buffer circuit is provided which includes: a buffer circuit which includes a first transistor and a second transistor; a first element which counts to a first value based on a clock signal and outputs the first counted value; a second element which counts to a second value based on the clock signal and outputs the second counted value; a third element which controls the first element based on an output from the buffer circuit; a fourth element which controls the second element based on an output from the buffer circuit; a fifth element which inputs the first counted value and controls impedance of the first transistor based on the first counted value; and a sixth element which input the second counted value and controls impedance of the second transistor based on the second counted value.
According to another aspect of the present invention, an output buffer circuit is provided which includes: a buffer circuit; and a first circuit which inputs a reference potential and the potential of an output of the buffer circuit and controls the buffer circuit so that the potential of the output of the buffer circuit becomes close to the reference potential.


REFERENCES:
patent: 5087834 (1992-02-01), Tsay
patent: 5485117 (1996-01-01), Furumochi
patent: 5568083 (1996-10-01), Uchiyama et al.
patent: 5789971 (1998-08-01), Colletti et al.
patent: 5892389 (1999-04-01), Lai
patent: 5973520 (1999-10-01), Maruyama
patent: 8-293780 (1996-11-01), None
patent: 9-261035 (1997-10-01), None

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