Output buffer circuit having a level conversion function

Details Output buffer circuit having a level conversion function Output buffer circuit having a level conversion function

1989-09-14

1991-08-27

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307451, 307455, H03K 19092, H03K 19094, H03K 19086, H03K 19003

Patent

active

050436040

ABSTRACT:
An output buffer circuit includes a prestage circuit which generates a first potential and a second potential (an intermediate voltage) based on the voltage of an input signal. The first potential is higher than the second potential. A final-stage circuit generates an output signal by controlling a current passing therethrough from a power source on the basis of the potential of the input terminal. The output signal is supplied to an ECL circuit through the output terminal. A control circuit generates a control signal during a predetermined time when a change in voltage of the input signal occurs. A bypass circuit sets the potential of the input terminal of the final-stage circuit lower than the second potential and discharging a parasitic capacitance coupled to the input terminal during the predetermined time defined by the control signal supplied from the control circuit when the prestage circuit outputs the second potential in response to a change in voltage of the input signal.

REFERENCES:
patent: 4450371 (1984-05-01), Bismarck
patent: 4453095 (1984-06-01), Wrathall
patent: 4563601 (1986-01-01), Asano et al.
patent: 4779013 (1988-10-01), Tanaka
patent: 4890019 (1989-12-01), Hoyte et al.
Patent Abstracts of Japan, vol. 12, No. 221 (E-625) [3068], 23rd Jun. 1988; & JP-A-63 15 522 (NEC Corp.), 22-01-1988 *Whole Document*.

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