Output buffer circuit for LSI circuit

Details Output buffer circuit for LSI circuit Output buffer circuit for LSI circuit

1991-07-24

1992-08-04

Pascal, Robert J.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307579, 307443, H03K 1900

Patent

active

051361914

ABSTRACT:
An output buffer circuit for an LSI circuit includes a control signal generating circuit, responsive to a signal at either one of first and second levels from an internal logic circuit for generating a control voltage at a level which is sufficient to reliably turn off the PMOSFET of a first CMOS circuit in the output buffer circuit. When the PMOSFET of the first CMOS circuit is turned off, a feedback circuit applies to the gate electrode of the PMOSFET, a signal at a level sufficient to maintain the PMOSFET in the non-conductive state regardless of changes in the control voltage while the signal from the internal logic circuit is at above-stated one level.

REFERENCES:
patent: 4851721 (1989-07-01), Okitaka
patent: 4888500 (1989-12-01), Nicollini et al.
patent: 5003205 (1991-03-01), Kohda
patent: 5023488 (1991-06-01), Gunning
patent: 5045730 (1991-09-01), Cooperman et al.
patent: 5073726 (1991-12-01), Kato et al.

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