Output buffer circuit capable of controlling through rate

Details Output buffer circuit capable of controlling through rate Output buffer circuit capable of controlling through rate

1998-09-24

2000-09-26

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

327112, 327391, 326 86, 326 87, H03K 1716, H03K 19003

Patent

active

061247472

ABSTRACT:
An output buffer circuit capable of controlling a through rate at a constant rate. Each decision circuit of a plurality of decision circuits (11-13, 18-20) receives a voltage potential from an output terminal (10) and compares it with a respective predetermined voltage value. Flip flops (15-17) with an asynchronous set function or flip flops (22-24) with an asynchronous reset function receive respective comparison results as decision results when receiving a respective trigger signal from a respective delay circuit from a plurality of delay circuits (14, 21) after the elapse of a respective predetermined time period from a time at which an input terminal (1) receives a H level control signal or an L level control signal. The flip flops (15-17 and 22-24) control the operation of output transistors (3-5 and 7-9) based on the respective decision results.

REFERENCES:
patent: 4829199 (1989-05-01), Prater
patent: 5122690 (1992-06-01), Bianchi
patent: 5134311 (1992-07-01), Biber et al.
patent: 5332932 (1994-07-01), Runaldue
patent: 5528166 (1996-06-01), Iikbahar

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