Output buffer circuit and method of operation thereof with reduc

Details Output buffer circuit and method of operation thereof with reduc Output buffer circuit and method of operation thereof with reduc

1991-09-17

1993-04-20

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 3072963, 307246, H03K 19092, H03K 1756

Patent

active

052045587

ABSTRACT:
An output buffer circuit comprises a P channel MOS transistor connected between a power supply terminal and an output terminal, an N channel MOS transistor connected between a ground terminal and an output terminal, a capacitance connected to a ground terminal, and a switch formed of an N channel MOS transistor connected between the output terminal and the capacitance. In charging a load, first, charge stored in the capacitance is supplied to the output terminal, and subsequently the P channel MOS transistor is turned on. In discharging the load, first, charge is supplied from the output terminal to the capacitance, and subsequently the N channel MOS transistor is turned on.

REFERENCES:
patent: 4499387 (1985-02-01), Konishi
patent: 4574203 (1986-03-01), Baba
patent: 4707623 (1987-11-01), Bismarck
patent: 4959565 (1990-09-01), Knecht et al.
patent: 4983861 (1991-01-01), Kikuchi et al.
patent: 5036227 (1991-07-01), Jo et al.

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