Output buffer circuit

Details Output buffer circuit Output buffer circuit

1984-03-23

1986-02-11

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307246, 307451, 307463, 307473, 307270, 307530, 307518, H03K 1704, H03K 17687, H03K 19096, H03K 5153

Patent

active

045700915

ABSTRACT:
An output buffer circuit has a data input terminal which receives logic data, load and drive transistors, a driver for selectively turning on the transistors in accordance with the logic value of the logic data, a data output terminal which is connected to a power source terminal of the VDD level through a current path of the load transistor and is grounded through a current path of the drive transistor, and a capacitor connected as a load to the data output terminal. The output buffer circuit further has a transistion detector circuit for generating a pulse signal in response to a change in level of each of address signals, and a preset circuit for supplying, in response to the pulse signal, a charge or discharge current to the capacitor while a voltage at the data output terminal is not at the VDD/2 level.

REFERENCES:
patent: 3909631 (1975-09-01), Kitagawa
patent: 3935476 (1976-01-01), Paluck
patent: 4465945 (1984-08-01), Yin
patent: 4488066 (1984-12-01), Shoji
patent: 4498021 (1985-02-01), Uya

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