Output buffer circuit

Details Output buffer circuit Output buffer circuit

2005-02-01

2005-02-01

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S437000

Reexamination Certificate

active

06850100

ABSTRACT:
An output buffer circuit of the invention comprises a first output transistor connected between a power supply potential node and an output node, a second output transistor connected between a ground potential node and the output node, a first control circuit for controlling a conductive state of the first output transistor, a first clamp circuit for supplying a given potential to a first node to which the first control circuit is connected, a control circuit for controlling a conductive state of the second output transistor, and a second clamp circuit for supplying a given potential to a second node to which the second control circuit is connected. The first clamp circuit supplies a given potential to the first node when the first control circuit is inactivated, and stops the supply of the given potential when the first control circuit is activated. The second clamp circuit supplies a given potential to the second node when the second control circuit is inactivated, and stops the supply of the given potential when the second control circuit is activated.

REFERENCES:
patent: 6400192 (2002-06-01), Boezen et al.
“Design Guide for a Low Speed Buffer For The Universal Serial Bus”, Intel Corporation, Revision 1.1, Dec. 1996, pp. 1-11.

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