Output buffer circuit

Details Output buffer circuit Output buffer circuit

2001-09-14

2004-01-06

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C326S086000

Reexamination Certificate

active

06674313

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to an output buffer circuit mounted on a semiconductor integrated circuit device, and converting logic data having been processed in the semiconductor integrated circuit device, into a logic signal, and outputting outwardly of the semiconductor integrated circuit device, and more particularly to such an output buffer circuit having a function of carrying out pre-emphasis in accordance with attenuation in a transmission line.
2. Description of the Related Art
Some of output buffer circuits for transmitting a logic signal to a transmission line acting as a distributed parameter circuit are designed to have a so-called pre-emphasis function by which a signal waveform is emphasized in accordance with attenuation in a signal on a transmission line. Such output buffer circuits are accomplished generally by a current-mode type circuit, that is, a circuit which deals with a signal indicative of a current.
The current-mode type circuit is accompanied with a problem that its structure causes the circuit to work not so well at a relatively low voltage.
However, as a technique for fabricating a semiconductor integrated circuit in a smaller scale has been developed, a semiconductor integrated circuit can work with lower power consumption because of reduction in an operational voltage. As a result, a semiconductor integrated circuit is presently requested to operate at a high rate at a lower voltage.
Japanese Unexamined Patent Publication No. 2000-68816 which is based on German patent application No. 19825258.7 filed on Jun. 5, 1998, for instance, has suggested an output buffer circuit to meet such a request.
The output buffer circuit suggested in the Publication is comprised of an output stage illustrated in
FIG. 1
, and a control circuit (not illustrated). The output stage illustrated in
FIG. 1
is comprised of n-channel field effect transistors N
11
, N
13
and N
15
each electrically connected between a higher voltage source VDD and an output terminal TOUT, n-channel field effect transistors N
12
, N
14
and N
16
each electrically connected between a lower voltage source VSS and the output terminal TOUT, and inverters INV
11
, INV
12
and INV
13
. The n-channel field effect transistors N
11
, N
13
and N
15
define a first impedance circuit, and the n-channel field effect transistors N
12
, N
14
and N
16
define a second impedance circuit.
The inverters INV
11
, INV
12
and INV
13
receive control signals A
1
, A
2
and A
3
, and inverted those control signals A
1
, A
2
and A
3
. The control signals A
1
, A
2
and A
3
are applied to gate electrodes of the n-channel field effect transistors N
11
, N
13
and N
15
, and the controls signals A
1
, A
2
and A
3
having been inverted by the inverters INV
11
, INV
12
and INV
13
are applied to gate electrodes of the n-channel field effect transistors N
12
, N
14
and N
16
. The n-channel field effect transistors N
11
, N
13
, N
15
, N
12
, N
14
and N
16
in the first and second impedance circuits are turned on or off such that an impedance ratio of an impedance of the first impedance circuit to an impedance of the second impedance circuit is equal to any one of at least three different values and that a sum of conductances of the first and second impedance circuits is not dependent on the impedance ratio. This ensures that an output impedance is kept almost equal to a predetermined value regardless of pre-emphasis.
Though the above-mentioned output buffer circuit can operate at a lower voltage than a voltage at which a general current-mode type circuit can operate, the output buffer circuit has to include the control circuit for controlling on/off of the field effect transistors constituting the first and second impedance circuits. The control circuit transmits the control signals A
1
, A
2
and A
3
required for a pre-emphasis step, by conducting logic operations such as logical product (AND) and logical sum (OR) through the use of data to be transmitted. As a result, the output buffer circuit unavoidably has much propagation delay time from an input to an output. An output signal is influenced by voltage source noises and voltage fluctuation during the propagation delay time, and thus, jitter is increased, resulting in that the output buffer circuit cannot operate at a high rate.
Japanese Unexamined Patent Publication No. 11-345054 has suggested a driver circuit for transmitting signals, including an output stage driver, a previous stage driver for driving the output stage driver, and a level adjuster for adjusting an output level of the previous stage driver. The output stage driver transmits a variable-level signal in accordance with the output level of the previous stage driver.
Japanese Unexamined Patent Publication No. 5-344026 has suggested a pre-emphasis circuit including an amplifying circuit equipped with a negative feed-back circuit which provided a smaller feed-back in response to a higher frequency.
Japanese Unexamined Patent Publication No. 7-183746 has suggested (a) an emphasis/de-emphasis circuit including an operational amplifier in which a de-emphasized signal input is input to a non-inverted input terminal, (b) a switching circuit having an input electrically connected to an output terminal of the operational amplifier, another input electrically connected to an emphasis input, and an output electrically connected to a de-emphasis signal output terminal, and equalizing the input and output to each other with respect to a voltage, selecting one of the input and another input, and transmitting the selected input, and (c) an emphasis circuit having an input electrically connected to an output of the switching circuit, and an output electrically connected to both the non-inverted input terminal of the operational amplifier and an emphasis signal output terminal, and conducting an emphasis step to signals received through the input. By means of the switching circuit, an emphasis step or a deemphasis step is carried out.
Japanese Unexamined Patent Publication No. 9-139664, which is based on United Kingdom patent application No. 9518183.0 filed on Sep. 6, 1995, has suggested an integrated circuit including a driver circuit which transmits data signals to communication channels. The driver circuit is comprised of a first output buffer including a plurality of pull-up transistors electrically connected to a first output conductor through pull-up resistors, and a plurality of pull-down transistors electrically connected to the first output conductor through pull-down resistors, a plurality of delay circuits each transmitting a delay data signal to each of control terminals of the pull-up and pull-down transistors, and control circuits operating one of the delay circuits selected in accordance with a data input signal.
Japanese Patent No. 2781137 (Japanese Unexamined Patent Publication No. 6-350961) has suggested a digital non-linear pre-emphasis circuit including a first filter which varies a gain in an input digital signal in accordance with an amplitude of a high frequency band of the input digital signal, and transmits a signal having the varied gain, a second filter which varies a band at which the signal output from the first filter can pass, in accordance with an amplitude of the signal output from the first filter, and a mixer which mixes the input digital signal with a signal output from the second filter, and transmits a pre-emphasized signal in which a high frequency band of the input signal is emphasized.
SUMMARY OF THE INVENTION
In view of the above-mentioned problems in the conventional output buffer circuit, it is an object of the present invention to provide an output buffer circuit which is capable of operating at a relatively low voltage in spite of having a function of pre-emphasis, and which has a shortened propagation delay time from an input to an output thereof.
There is provided an output buffer circuit having a function of accomplishing pre-emphasis, and transmitting a logic signal to a transmission line acting as a d

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