Output buffer circuit

Details Output buffer circuit Output buffer circuit

2001-06-25

2003-02-25

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S112000

Reexamination Certificate

active

06525575

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to a semiconductor circuit and more particularly to an output buffer circuit used for outputting a signal.
BACKGROUND OF THE INVENTION
A conventional buffer circuit can be controllable by a received control signal in a manner that it is enabled when the control signal is in one logic state and is disabled when the control signal is in another logic state.
One such conventional buffer circuit is illustrated in FIG.
1
and given the general reference character
200
. Conventional buffer circuit
200
is a 3-state buffer circuit in that it can output a logic one (first state), a logic zero (second state) or can be placed in a high impedance state (third state). Conventional buffer circuit
200
includes a selector
201
and a buffer
202
.
Selector
201
includes transfer gates (
203
and
204
). Transfer gate
203
consists of N-channel metal-oxide-semiconductor (NMOS) transistor
205
, P-channel metal-oxide-semiconductor (PMOS) transistor
206
and inverter
207
. Similarly, transfer gate
204
consists of NMOS transistor
208
, PMOS transistor
209
and inverter
210
.
Selector
201
responds to select signals (SEL
1
and SEL
2
) to output one of data input signals (DATAIN
1
or DATAIN
2
) as data signal DATAIN to buffer
202
.
Buffer
202
includes NAND gate
211
, PMOS transistor
212
, NOR gate
213
, inverter,
214
, and NMOS transistor
215
. Conventional buffer circuit
200
is a complementary MOS (CMOS) circuit that is typical in existing semiconductor devices.
NAND gate
211
receives data signal DATAIN and control signal SELB as inputs. NAND gate
211
provides an output to a gate of PMOS transistor
212
. NOR gate
213
receives data signal DATAIN as one input and receives control signal SELB through inverter
214
as another input. NOR gate
213
provides an output to a gate of NMOS transistor
215
.
When control signal SELB is at a high logic level (i.e. power supply potential), buffer
202
provides an output signal DATAOUT at output terminal
216
that has the same logic level as data signal DATAIN. However, when control signal SELB is at a low logic level (i.e. ground potential), buffer
202
sets output terminal
216
to a high impedance state.
It is noted that when providing a logic low on output signal DATAOUT, the gate of NMOS transistor
215
must be pulled high by NOR gate
213
. Because the load on output signal DATAOUT can be large, NMOS transistor
215
is typically a large device. Thus, NOR gate
213
must pull a relatively large capacitive node to a high level. This can inhibit the speed of operation of the buffer
202
, as will be explained in more detail with reference to FIG.
2
.
Referring now to
FIG. 2
, a circuit diagram of NOR gate
213
is set forth. NOR gate
213
is a conventional CMOS NOR gate that is widely used in existing semiconductor devices.
NOR gate
213
consists of PMOS transistors (
221
and
222
) and NMOS transistors (
223
and
224
). Input terminal
225
is connected to the gate of PMOS transistor
221
and the gate of NMOS transistor
223
. Input terminal
226
is connected to the gate of PMOS transistor
222
and NMOS transistor
224
. The source of PMOS transistor
221
is connected to power supply terminal
229
. The drain of PMOS transistor
221
is connected to the source of PMOS transistor
222
. The drain of PMOS transistor
222
is connected to output terminal
227
. NMOS transistors (
223
and
224
) each have a source connected to ground terminal
228
and a drain connected to output terminal
227
. Power supply terminal
229
is fixed to a power supply potential Vcc. Ground terminal
228
is fixed to ground potential.
When output terminal
227
is pulled to a high level, power supply potential is supplied to output terminal
227
through series connected PMOS transistors (
221
and
222
).
Thus, the gate of NMOS transistor
215
(
FIG. 1
) is pulled high through two series connected PMOS transistors (
221
and
222
) in NOR gate
213
. Series connected PMOS transistors have only one-half the current drive as a single PMOS transistor of the same size. Also, PMOS transistors have a lower conductivity than NMOS transistors due to the differing mobility between holes and electrons. In order to increase the driving capability of the two series connected PMOS transistors (
221
and
222
) in NOR gate
213
each PMOS transistor must have a gate width that is double the gate width to get similar driving capabilities as a single PMOS transistor. However, this increases the load on logic gates in the previous stage, which can result in reduced circuit operational speeds. In order to compensate for this, further increases in device sizes in previous logic stages may be needed, which increases overall chip size and increases production costs.
In view of the above discussion, it would be desirable to provide a buffer circuit having a reduced time required for outputting data. It would also be desirable to provide a buffer circuit, which is capable of selectively outputting a plurality of data and having a reduced time required for outputting data.
SUMMARY OF THE INVENTION
According to the present embodiments, an output buffer circuit having an output time, which may be reduced is provided. The output buffer circuit may include a selector, a precharge circuit, and a buffer. The selector may be responsive to a control signal and may provide data on a data signal line. Precharge circuit may be responsive to the control signal and may precharge the data signal line to a first potential when the control signal is in a disable state. The selector may electrically disconnect data input terminals from the data signal line when the control signal is in the disable state. The buffer may output a logic value from the data signal line when the control signal is in an enable state.
According to one aspect of the embodiments, the control signal may have a control signal enable state and a control signal disable state. The selector circuit may be enabled to output a data signal to the data signal line in response to the control signal having the control signal enable state.
According to another aspect of the embodiments, the selector circuit may be disabled to output a data signal to the data signal line in response to the control signal having the control signal disable state.
According to another aspect of the embodiments, a precharge circuit may precharge the data signal line to a first potential when the control signal is in the disable state.
According to another aspect of the embodiments, the first potential may be approximately equal to a power supply potential.
According to another aspect of the embodiments, the selector circuit may be coupled to receive a plurality of data input signals and at least one select signal and may select one of the plurality of data input signals to output on the data signal line according to the at least one select signal.
According to another aspect of the embodiments, the selector circuit may be coupled to receive a single data input signal and may output the single data input signal on the data signal line in response to the control signal.
According to another aspect of the embodiments, the precharge circuit can include a precharge insulated gate field effect transistor (IGFET) providing a low impedance path between a power supply terminal and the data signal line in response to the control signal having the control signal disable state and a high impedance path between the power supply terminal and the data signal line in response to the control signal having the control signal enable state.
According to another aspect of the embodiments, the precharge IGFET may be a p-type IGFET and the power supply terminal may receive a power supply potential that is approximately equal to the first potential.
According to another aspect of the embodiments, the precharge IGFET may be an n-type IGFET and the power supply terminal may receive a power supply potential that is at least one n-type IGFET threshold voltage greater than the first potential.
Accord

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