Output buffer circuit

Details Output buffer circuit Output buffer circuit

1999-10-21

2003-07-01

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S112000

Reexamination Certificate

active

06586973

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to an output buffer circuit.
DESCRIPTION OF THE BACKGROUND ART
FIG. 14
is a circuit diagram showing the operating principles of a conventional output buffer circuit with slew-rate controlling capability. As shown, high output transistors QP
21
through QP
24
and low output transistors QN
21
through QN
24
are provided in four stages between an input terminal
91
and an output terminal
92
. Sources of the high output transistors QP
21
through QP
24
are all connected to the power supply. Their drains are connected to drains of the low output transistors QN
21
through QN
24
, respectively, and in common to the output terminal
92
. Sources of the low output transistors QN
21
through QN
24
are all grounded.
An input signal IN received from the input terminal
91
is applied to a gate of the high output transistor QP
21
and delay circuits
111
and
121
. Delay circuits
111
through
113
are connected in series and delay circuits
121
through
123
are connected in series. Each delay circuit delay the input signal IN by a predetermined time interval.
Output signals from the delay circuits
111
,
112
, and
113
are applied to gates of the high output transistors QP
22
, QP
23
, and QP
24
, respectively.
Output signals from the delay circuits
121
,
122
, and
123
are applied to gates of the low output transistors QN
22
, QN
23
, and QN
24
, respectively.
In this circuit configuration, the delay circuits
111
through
113
cause a time lag among the high output transistors QP
21
through QP
24
so that the input signal IN is sequentially applied to the gates of the transistors QP
21
through QP
24
in this order. Also, the delay circuits
121
,
122
, and
123
cause a time lag among the low output transistors QN
21
through QN
24
so that the input signal IN is sequentially applied to the gates of the transistors QN
21
through QN
24
in this order.
When the input signal IN makes a HIGH to LOW or LOW to HIGH transition, the high output transistors QP
21
through QP
24
or the low output transistors QN
21
through QN
24
are turned on in sequence after a time lag. Thus, slew rate of an output signal OUT during periods of relatively heavy load on the output terminal
92
is brought close to that during periods of relatively light load on the output terminal
92
.
By raising the slew rate during periods of relatively heavy load on the output terminal
92
, the conventional output buffer circuit has relieved a difference in the slew rate of the output signal OUT due to changes of the load on the output terminal
92
.
However, even if the transistor characteristics change according to load capacity of the output terminal
92
or ambient temperature, the delay circuits
111
through
113
and the delay circuits
121
through
123
cause a constant time lag among the high output transistors QP
21
through QP
24
and the low output transistors QN
21
through QN
24
, respectively. Therefore, the conventional output buffer circuit in
FIG. 14
has been posing a problem of the occurrence of variations in the slew rate of output waveforms of the output signal OUT due to changes of the load on the output terminal
92
, as indicated by P
1
through P
4
in FIG.
4
.
Another problem is high current consumption. That is, even if the load on the output terminal
92
is light enough to achieve good slew rate only with a single inverter, the conventional output buffer circuit turns on the four transistors in sequence, which is equivalent to driving four inverters in sequence. This requires extra current.
SUMMARY OF THE INVENTION
A first aspect of the present invention is directed to an output buffer circuit comprising: an input terminal receiving an input signal; an output terminal outputting an output signal; a delay circuit for delaying the input signal by a delay time to output a delay signal, the delay time varying according to a potential of the output signal; and an output buffer portion for outputting the output signal in response to a relative input signal correlated with the input signal, the output buffer portion receiving a relative delay signal correlated with the delay signal, a driving capability of the output buffer portion to the relative input signal varying according to the delay time.
According to a second aspect of the present invention, in the output buffer circuit of the first aspect, the delay time includes a plurality of delay times; the delay signal includes a plurality of delay signals obtained by delaying the input signal by the plurality of delay times; the output buffer portion includes a plurality of buffer portions provided in a one-to-one correspondence with the plurality of delay signals, for outputting the output signal in response to the plurality of delay signals; and the relative input signal and the relative delay signal are the same signal including the plurality of delay signals.
According to a third aspect of the present invention, in the output buffer circuit of the first aspect, the relative input signal includes the input signal, the output buffer circuit further comprising: a plurality of data storage portions for storing control data, each receiving the delay signal at a different input time that elapses from a logic level transition on the input signal, and if the delay signal makes the logic level transition, setting the control data to indicate a halt in the operation of the output buffer, wherein the relative delay signal includes the control data in the plurality of data storage portions; wherein the output buffer portion includes a plurality of buffer portions provided in a one-to-one correspondence with the plurality of data storage portions, the operating/halting status of each of the plurality of output buffer portions being determined on the basis of the control data stored in a corresponding data storage portion.
According to a fourth aspect of the present invention, in the output buffer circuit of the first aspect, the input signal has first and second logic levels; and the output buffer portion includes a first logic output portion for setting the output signal to the first logic level under operating conditions on the basis of the relative delay signal, and a second logic output portion for setting the output signal to the second logic level under operating conditions on the basis of the relative delay signal. The output buffer circuit further comprises: a first logic output control portion for bringing the first logic output portion into operation when the input signal makes a first transition from the second logic level to the first logic level; and a second logic output control portion for bringing the second logic output portion into operation when the input signal makes a second transition from the first logic level to the second logic level.
According to a fifth aspect of the present invention, the output buffer circuit of the third aspect further comprises an input time setting portion for setting the input time of each of the plurality of data storage portions on the basis of a plurality of RC delay signals obtained by delaying the input signal with RC time constant.
According to a sixth aspect of the present invention, the output buffer circuit of the third aspect further comprises an output buffer starting portion for activating the output buffer portion at a time when a predetermined condition is satisfied, by setting the control data in the plurality of storage portions to indicate the operation of the output buffer.
According to a seventh aspect of the present invention, in the output buffer circuit of the sixth aspect, the time when the predetermined condition is satisfied includes a time of power-on and a time of reset.
According to an eighth aspect of the present invention, in the output buffer circuit of the sixth aspect, the output buffer starting portion has a timer function, for monitoring a state of the output signal at predetermined time intervals and activating the output buffer portion at a time when the state of the output signal does not sa

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