Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
2000-09-27
2001-11-20
Nuton, My-Trang (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C327S112000
Reexamination Certificate
active
06320432
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an output buffer circuit which is built in a semiconductor integrated circuit to yield an output signal of a predetermined level such as a high or low level in accordance with the level of the input signal.
2. Description of the Prior Art
FIG. 17
is a circuit diagram showing a conventional output buffer circuit, which is denoted generally by
100
. Reference character A denotes an input signal which is applied to an input terminal; OE denotes an output enable signal which is applied to an output enable signal input terminal of the output buffer circuit
100
; OUT denotes an output signal which is provided at the output terminal of the output buffer circuit
100
;
101
denotes a P-channel transistor which functions as an output transistor for providing an high-level output signal;
102
denotes an N-channel transistor which functions as an output transistor for providing a low-level output signal;
103
denotes a NAND circuit;
104
denotes a NOR gate; and
105
and
106
denote inverters.
The operation of the prior art example will be described below in brief.
FIG. 18
is a graph for explaining the operation of the conventional output buffer circuit
100
depicted in FIG.
17
. Upon input of the input signal A of the high-level to the input terminal when the output enable signal OE input to the output enable signal input terminal is high-level, the P-channel transistor
101
turns ON, and provides a high-level output signal OUT to the output terminal. Similarly, upon input of the input signal A of the low-level when the output enable signal OE is high-level, the N-channel transistor
102
turns ON, and provides a low-level output signal OUT.
In this instance, since the driving power of each of the P- and N-channel output transistors
101
and
102
is constant, a change in the load capacitance connected to the output terminal causes a change in the time in which the potential of the output signal from the output terminal reaches a predetermined high or low level. For example, as depicted in
FIG. 1
, when the load capacitance connected to the output terminal increases, the time for the potential of the output signal OUT to reach the high level becomes longer because of the fixed driving power of the P-channel transistor
101
.
With the driving power of each output transistor heightened to solve this problem, however, when the load capacitance is small, the potential of the output signal OUT sharply changes to a predetermined level—this gives rise to a problem that an overshoot or undershoot of the output signal OUT is not suppressed. On the other hand, lowering of the driving power of the output transistor causes the problem of an increase in the time for the potential of the output signal OUT to reach a predetermined level when the load capacitance is larger.
FIG. 19
is a circuit diagram showing another conventional output buffer circuit, indicated generally by
110
, which is identical in construction with the
FIG. 17
example except that a capacitance C is connected between a node interconnecting gates of the P- and N-channel transistors
101
and
102
and the output terminal. Shown below the output buffer circuit
110
is its equivalent circuit with the output enable signal OE at the high level.
The output buffer circuit
110
of
FIG. 19
is so configured as to settle the problem that the output buffer circuit
100
of
FIG. 17
encounters. That is, the capacitance C is used to detect the potential at the output terminal. For example, when the potential of the output signal OUT varies, the potential is fed back to the gates of the P- and N-channel transistors
101
and
102
via the capacitance C. Accordingly, when the load capacitance connected to the output terminal changes in magnitude, the potential of the output signal OUT is transferred to the P- and N-channel transistors
101
and
102
via the capacitance C to control their operation and hence control the driving power of the output buffer circuit
110
.
FIG. 20
is a block diagram depicting an input/output circuit in which there is incorporated the output buffer circuit
110
of FIG.
19
. Reference numeral
110
denotes the output buffer circuit depicted in
FIG. 19
;
111
denotes an input buffer circuit; A denotes an input signal to an input terminal; OE denotes an output enable signal; Y denotes an output signal at an output terminal; IE denotes an input/output enable signal; and INOUT denotes an input/output circuit In the input/output circuit of
FIG. 20
, even when the output enable signal OE is not at the high level indicating that the output buffer circuit
110
is in the output state, that is, even when the output enable signal OE is low-level, a potential change at the input/output terminal INOUT triggers turning ON of the P- or N-channel transistor
101
or
102
via the capacitance C, leading to a malfunction.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an output buffer circuit which enables the potential of its output signal to reach a predetermined value within a fixed time, that is, suppresses overshooting and undershooting of the output signal, even if the load capacitance connected to the output terminal undergoes a variation.
Another object of the present invention is to provide an output buffer circuit which will not malfunction even when built in an input/output circuit.
According to an aspect of the present invention, there is provided an output buffer circuit which comprises: an output transistor which supplies a voltage to an output signal to be output from an output terminal in accordance with the level of an input signal fed via an input terminal; a capacitance for detecting the potential of the output signal; feedback control means formed by a transistor and connected between the capacitance and the output transistor, for feeding back the potential of the output signal detected by the capacitance to control the gate potential of the output transistor and control the driving power of the output transistor so that the output signal reaches a predetermined level in a fixed time regardless of a change in the capacitance of a load connected to the output terminal; and a control transistor for turning OFF the operation of the feedback means when the output signal is not output.
According to another aspect of the present invention, the output transistor is a P-channel transistor for supplying a high-level voltage to the output signal when it is high-level, and the output transistor is an N-channel transistor for supplying a low-level voltage to the output signal when it is low-level.
According to another aspect of the present invention, the output transistor is an N-channel transistor for supplying a high-level voltage to the output signal when it is high-level, and the output transistor is a N-channel transistor for supplying a low-level voltage to the output signal when it is low-level.
According to another aspect of the present invention, the capacitance comprises a first capacitance for detecting the voltage of the output signal when it is high-level and a second capacitance for detecting the voltage of the output signal when it is low-level.
According to another aspect of the present invention, the output buffer circuit further comprises: a third capacitance connected in parallel to the first or second capacitance and having a capacitance value different from that of the first or second capacitance; and a first selector for selecting any one of the first, second and third capacitances.
According to another aspect of the present invention, the feedback control means further comprises: a plurality of transistors connected in series between the gate of the output transistor for generating a high- or low-level output signal and the ground, for feeding back the potential of the output signal detected by the first or second capacitance to the output transistor, and a second selector for selecting either one of the transistors to change the size of the transisto
Burns Doane , Swecker, Mathis LLP
Mitsubishi Denki & Kabushiki Kaisha
Nuton My-Trang
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