Output buffer circuit

Details Output buffer circuit Output buffer circuit

1997-02-28

1998-10-20

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

327112, 327379, 327384, 327389, 326 26, 326 27, 326 82, 326 83, 326 87, H03K 301

Patent

active

058252150

ABSTRACT:
An output buffer circuit of the present invention comprises a first input terminal receiving a first input signal, a second input terminal receiving a second input signal, a control input terminal receiving a control signal, an output terminal outputting an output signal, a first transistor coupled between the output node and a first potential source and a second transistor coupled between the output node and a second potential source. The output buffer of the present invention further includes a first gate circuit and a second gate circuit. The first gate circuit has a first input node coupled to receive the first input signal, a second input node coupled to receive the control signal, an enable input node coupled to receive the second input signal and an output node coupled to the control terminal of the first transistor. The first gate circuit outputs the signal received by the enable input node when the signals received by the first and second input nodes have predetermined level. The second gate circuit has a first input node coupled to receive the second input signal, a second input node coupled to receive the control signal, an enable input node coupled to receive the first input signal and an output node coupled to the control terminal of the first transistor. The second gate circuit has the same circuit configuration of the first gate circuit.

REFERENCES:
patent: 5001369 (1991-03-01), Lee
patent: 5075569 (1991-12-01), Branson
patent: 5341338 (1994-08-01), Hashiguchi et al.
patent: 5508635 (1996-04-01), Kwon
patent: 5629634 (1997-05-01), Carl et al.

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