Output buffer circuit

Details Output buffer circuit Output buffer circuit

1999-11-15

2001-07-17

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S170000, C327S379000

Reexamination Certificate

active

06262607

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an output buffer circuit used in a semiconductor integrated circuit. More particularly, this invention relates to a CMOS output buffer circuit.
BACKGROUND OF THE INVENTION
In recent years, with an increase in speed of a digital signal processing, a high processing speed is also demanded in an output buffer circuit. As a conventional output buffer circuit, an output buffer circuit having a complementary metal oxide semiconductor (CMOS) configuration using a transistor having a high current drive capability for increasing processing speed is known.
FIG. 14
is a circuit diagram showing a rough configuration of a conventional output buffer circuit. The conventional output buffer circuit comprises an inverter circuit
91
serving as a pre-driver and a final CMOS output circuit in which a p-channel MOS transistor QP
0
having a high drive capability and an n-channel MOS transistor QN
0
are connected in series with each other. A load capacitor CL is connected to the output terminal of the final CMOS output circuit extracted from the node between the p-channel MOS transistor QP
0
and the n-channel MOS transistor QN
0
.
Operation of the conventional output buffer circuit will be described below.
FIG. 15
is a timing chart showing the operation of the conventional output buffer circuit. In the operation of the conventional output buffer circuit, when an input signal Vin input to the inverter circuit
91
is at an “L” level, an output signal A
0
from the inverter circuit
91
goes to an “H” level, the p-channel MOS transistor QP
0
is turned OFF, and the n-channel MOS transistor QN
0
is turned ON. In this manner, the load capacitor CL is in a discharge state, and an output signal Vout
0
from the output buffer goes to an “L” level.
When the level of the input signal Vin changes from an “L” level to an “H” level, the level of the output signal A
0
from the inverter circuit
91
changes from an “H” level to an “L” level, the p-channel MOS transistor QP
0
is turned ON, and the n-channel MOS transistor QN
0
is turned OFF. In this manner, the load capacitor CL is charged, and the output signal Vout
0
goes to an “H” level. In addition, the level of the input signal Vin changes from an “H” level to an “L” level again, the level of the output signal A
0
from the inverter circuit
91
changes from an “L” level to an “H” level, the p-channel MOS transistor QP
0
is turned OFF, and the n-channel MOS transistor QN
0
is turned ON. In this manner, electric charges charged in the load capacitor CL are discharged, and the output signal Vout
0
goes to an “L” level.
In order to increase the processing speed of the output buffer circuit, the current drive capabilities of the p-channel MOS transistor QP
0
and the n-channel MOS transistor QN
0
serving as output transistors are made high. In this case, when the load capacitor CL is large, the inductances of the load capacitor CL and a wire or the like resonate. When the output signal Vout
0
rises or drops, overshoot, undershoot, and ringing occur. The principle behind the occurrence of ringing and the like occur will be described below with reference to FIG.
16
.
FIG. 16
is a circuit diagram showing a rough equivalent circuit of the conventional output buffer circuit in a state wherein a signal having an “L” level is output, i.e., the n-channel MOS transistor QN
0
is turned ON.
In the equivalent circuit of the conventional output buffer circuit, the n-channel MOS transistor QN
0
is represented by a circuit in which a current source
92
and an ON resistor Ron are connected in parallel to each other. A load connected to an output terminal
93
of the output buffer circuit is expressed by a circuit obtained such that an inductance
94
constituted by a wire, a pattern on a printed board, a bonding wire of an integrated circuit, or the like is connected in series with a load capacitor
95
. In this manner, an equivalent circuit including the output buffer circuit and the load constitutes an LCR resonance circuit. A resonance frequency f
0
of the LCR resonance circuit and a value &thgr; obtained at the resonance frequency are expressed by the following equations:
f0=1/(2&pgr;·SQRT(LC))
 &thgr;=j&ohgr;0·L/Ron
where 2&pgr;f0=&ohgr;0, and SQRT(X) represents the square root of X.
In this case, as the current drive capability of the output transistor is increased to increase the processing speed of the output buffer circuit, the ON resistor Ron of the output transistor decreases. Accordingly, the value &thgr; increases and the output buffer circuit resonates due to a change in level of the input signal Vin
0
from an “H” level to an “L” level, so that ringing or the like of the output signal Vout
0
occurs.
However, according to the prior art described above, when the current drive capability of the output transistor is excessively increased to increase the processing speed of the output buffer circuit, overshoot, undershoot, and ringing occur when the output signal Vout
0
rises or drops. The overshoot, undershoot, and ringing may generate noise in signal transmission, and may cause an erroneous operation of a logic circuit system. In addition, the overshoot, undershoot, and ringing may be a factor called an undesired reflection which generates jamming waves to another electronic equipment. Thus, an increase in current drive capability of the output transistor is limited to a specific level, and a desired high-speed operation cannot be performed.
SUMMARY OF THE INVENTION
The present invention has been made in consideration of the above circumstances. It is an object of this invention to obtain a high-speed output buffer circuit which reduces overshoot, undershoot, and ringing of an output signal to prevent an erroneous operation and has a high drive capability.
According to a first aspect of the present invention, a correction unit decrease a signal output by an output unit when the signal rises from a relatively low first potential level (“L” level) to a relatively high second potential level (“H” level), and temporarily raises the signal when the signal falls from the relatively high second potential level to the relatively low first potential level. In this manner, when the output signal rises, a voltage applied to the gate of the output unit is temporarily increased immediately before overshoot occurs and hence the output signal can be suppressed from rising. When the output signal falls, a voltage applied to the gate of the output unit is temporarily decreased immediately before undershoot occurs and hence the output signal can be suppressed from falling.
According to second aspect of the present invention, a correction unit temporarily gives a reverse bias to suppress an output signal of the output buffer circuit from rising when a signal output by an output unit rises from a relatively low first potential level to a relatively high second potential level, and temporarily gives a reverse bias to suppress the output signal of the output buffer circuit from falling when the signal output by the output unit falls from the relatively high second potential level to the relatively low first potential level. In this manner, when the output signal rises, the output signal can be temporarily suppressed from rising immediately before overshoot occurs. When the output signal falls, the output signal can be temporarily suppressed from falling immediately before undershoot occurs.
In the invention according to first and second aspects of the present invention, the timing at which the signal output by the output unit is temporarily decreased or raised or the timing at which the output signal of the output buffer circuit is suppressed from rising or falling is adjusted by a first adjustment unit. Therefore, the signal output by the output unit can be temporarily controlled to decrease or raise, or the output signal of the output buffer circuit can be suppressed from falling or rising at an appropriate timing depending upon the characteristics (capacitance and the like) of

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