Output buffer circuit

Details Output buffer circuit Output buffer circuit

1999-10-22

2001-05-22

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S310000, C327S312000, C326S027000, C326S083000

Reexamination Certificate

active

06236248

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an output buffer circuit for digital signals and more particularly, to an output buffer circuit having a pair of p- and n-channel Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) in its output stage, which suppresses a peak current flowing through the pair of MOSFETs and operates at high switching rate.
2. Description of the Prior Art
Input and output buffer circuits have been popularly used in Very Large Scale Integrated circuits (VLSIs) for exchanging digital signals with respect to their outside circuitry.
An output buffer circuit receives a digital input signal and outputs a digital output signal for driving its external load, thereby setting the logic state of the external load at a logic low (L) level or a logic high (H) level according to the logic state of the applied input signal. When the output signals of a plurality of output buffer circuits in a VLSI are simultaneously switched to the same logic level L or H, the magnitude of the power supply current flowing through the VLSI changes largely and rapidly, resulting in noise in the VLSI due to the transient phenomena of the currents and/or voltages. This noise tends to cause malfunction of other circuits connected to the same power supply as that of the output buffer circuit, such as input buffer circuits. Therefore, to prevent this malfunction problem from occurring, a solution that the slew rate (i.e., the maximum rate of change with respect to an applied square or stepped wave) of the output signal of the output buffer circuit is suitably adjusted has been developed and practically used.
On the other hand, it is needless to say that output buffer circuits of this sort are required to operate or switched as fast as possible.
An example of prior-art output buffer circuits of this sort is disclosed in the Japanese Non-Examined Patent Publication No. 9-148909 published in June 1997, in which the control voltages applied to the gates of MOSFETs located in the output stage are adjusted to change rapidly and then, to change slowly at each switching operation of the MOSFETs.
FIG. 1
shows the circuit configuration of the prior-art output buffer circuit disclosed in the Japanese Non-Examined Patent Publication No. 9-148909.
As shown in
FIG. 1
, this prior-art output buffer circuit is comprised of p- and n-channel output MOSFETs M
130
and M
140
, first and second threshold detection circuits T
131
, and T
132
, first and second switches S
101
and S
102
, first and second resistors R
131
and R
141
, p- and n-channel MOSFETs M
131
and M
132
forming a first Complementary MOS (CMOS) inverter, p- and n-channel MOSFETs M
141
and M
142
forming a second CMOS inverter, and input and output terminals
102
and
103
. A digital input signal D
IN
is applied to the input terminal
102
and a digital output signal D
OUT
having the same logic state as that of the input signal D
IN
is derived from the output terminal
103
. The reference symbol V
CC
denotes a power supply voltage.
The first and second CMOS inverters formed by the MOSFETs M
131
, M
132
, M
141
, and M
142
constitute a previous stage
101
for inverting the input signal D
IN
and outputting an inverted one of the input signal D
IN
. The p- and n-channel output MOSFETs M
130
and M
140
constitute a CMOS output stage
104
for inverting the inverted signal from the previous stage
101
and outputting the digital output signal D
OUT
having the same logic state as that of the input signal D
IN
.
The first resistor R
131
, the first switch circuit S
101
, and the first threshold detection circuit T
131
constitute a first slew-rate control circuit for controlling the changing rate of the gate voltage V
G130
of the p-channel MOSFET M
130
in the output stage
104
. The first resistor R
131
suppresses the rate of falling behavior from the logic H state to the logic L state of the gate voltage V
G130
(i.e., the pull-down operation of the MOSFET M
130
). The first switch S
101
forms a bypass of the first resistor R
131
, which is turned on or off under the control of the first threshold detection circuit T
131
. The first threshold detection circuit T
131
detects whether the gate voltage V
G130
of the p-channel MOSFET M
130
is equal to or lower than the threshold voltage V
THP
at which the MOSFET M
130
is switched from the OFF state to the ON state. Thus, when the gate voltage V
G130
of the p-channel MOSFET M
130
is equal to or lower than the threshold voltage V
THP
, the first threshold detection circuit T
131
turns the first switch S
101
off. When the gate voltage V
G130
of the p-channel MOSFET M
130
is higher than the threshold voltage V
THP
, the first threshold detection circuit T
131
turns the first switch S
101
on.
The second resistor R
141
, the second switch circuit S
102
, and the second threshold detection circuit T
141
constitute a second slew-rate control circuit for controlling the changing rate of the gate voltage V
G140
of the n-channel MOSFET M
140
in the output stage
104
. The second resistor R
141
suppresses the rate of rising behavior from the logic L state to the logic H state of the gate voltage V
G140
(i.e., the pull-up operation of the MOSFET M
140
). The second switch S
102
forms a bypass of the second resistor R
141
, which is turned on or off under the control of the second threshold detection circuit T
141
. The second threshold detection circuit T
141
detects whether the gate voltage V
G140
of the n-channel MOSFET M
140
is equal to or higher than the threshold voltage V
THN
at which the MOSFET M
140
is switched from the OFF state to the ON state. Thus, when the gate voltage V
G140
of the n-channel MOSFET M
140
is equal to or higher than the threshold voltage V
THN
, the second threshold detection circuit T
141
turns the second switch S
102
off. When the gate voltage V
G140
of the n-channel MOSFET M
140
is lower than the threshold voltage V
THN
, the second threshold detection circuit T
141
turns the second switch S
102
on.
The prior-art output buffer circuit shown in
FIG. 1
operates in the following way:
When the input signal D
IN
applied to the input terminal
102
is changed from the logic L state to the logic H state, the gate voltages V
G130
and V
G140
of the MOSFETs M
130
and M
140
in the output stage
104
are pulled down by the first and second CMOS inverters formed by the MOSFETs M
131
and M
132
and M
141
and M
142
in the previous stage
101
, respectively. In this case, the p-channel MOSFET M
130
is switched from the OFF state to the ON state, because the decreased (i.e., pulled-down) gate voltage V
G130
of the MOSFET M
130
becomes lower than its threshold voltage V
THP
. During this switching operation of the MOSFET M
130
, the first switch S
101
is switched from the ON state to the OFF state by the first threshold detection circuit T
131
at the time when the gate voltage V
G130
of the MOSFET M
130
is lowered to be equal to the threshold voltage V
THP
, thereby inserting the first resistor R
131
into the path connecting the drains of the MOSFETs M
131
and M
132
of the first CMOS inverter. Thus, the decreasing rate of the threshold voltage V
THP
is suppressed.
As a result, when the input signal D
IN
is changed from the logic L state to the logic H state, the decreasing rate of the gate voltage V
G130
of the MOSFET M
130
is relatively higher until the gate voltage V
G130
is lowered to be equal to the threshold voltage V
THP
, and is relatively lower after the gate voltage V
G130
is lower than the threshold voltage V
THP
.
On the other hand, the n-channel MOSFET M
140
in the output stage
104
is switched from the ON state to the OFF state, because the decreased (i.e., pulled-down) gate voltage V
G140
of the MOSFET M
140
becomes lower than its threshold voltage V
THN
. During this switching operation, the second switch S
102
is kept in the ON state and accordingly, the drains of the MOSFETs M
141
and M
142
of the second CMOS inverter are directly connected to each ot

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