Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Slope control of leading or trailing edge of rectangular or...
Reexamination Certificate
1999-03-19
2001-01-30
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Slope control of leading or trailing edge of rectangular or...
C326S026000, C326S027000
Reexamination Certificate
active
06181176
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an output buffer circuit, more particularly, to an output buffer circuit which outputs an output signal whose slew rate has changed.
A conventional output buffer circuit of this kind, which outputs an output signal whose slew rate has changed, is connected to a bus and transmits the output signal. Such a conventional output buffer circuit is, for example, an open drain type and is used in a high-speed bus such as Gunning Transceiver Logic (GTL) or the like. The change of the slew rate is performed to prevent the influence of reflection via the bus.
Referring to
FIG. 4
, a conventional output buffer circuit has: a negative channel metal-oxide semiconductor (NMOS) transistor
430
in which a drain terminal
4302
is connected to a transfer path
440
; and a slew rate control circuit
410
connected to a gate terminal
4301
of NMOS transistor
430
. Slew rate control circuit
410
inputs an input signal IN and outputs a signal after adjusting the slew rate of rise or fall of signal IN. An output signal from slew rate control circuit
410
is inputted to gate terminal
4301
of NMOS transistor
430
.
FIG. 5
shows the adjusted rise and fall slew rate of the output signal outputted from slew rate control circuit
410
. The slew rate of an output signal from NMOS transistor
430
, which is outputted to an output terminal
431
, can also be changed. In
FIG. 5
, the slew rate is adjusted to decrease in order from the dotted line, to the dashed line and to the solid line.
An example of such a conventional output buffer circuit is disclosed in Japanese Unexamined Patent Publication No. Hei 8-63267.
The above-described conventional output buffer circuit creates a problem when the output signal from NMOS transistor
430
falls because the operation start time of NMOS transistor
430
differs when the slew rate is fast and when the slew rate is slow (hereinafter, the time difference is referred to as offset time). NMOS transistor
430
is off during a time period in which a voltage value of the output signal from slew rate control circuit
410
stays in a range from 0 V through threshold value voltage Vt and turns on only after the voltage value exceeds the threshold value voltage Vt. Therefore, when the inclination of the output signal from slew rate control circuit
410
becomes small, it takes time until the voltage value exceeds the threshold value voltage Vt.
Furthermore, the above-described conventional output buffer circuit creates another problem when the output signal from NMOS transistor
430
rises, although the offset time problem mentioned above does not occur, because the time period until the output signal rises is delayed when the slew rate of the output signal from NMOS transistor
430
is adjusted to be small. This is because an output level of slew rate control circuit
410
is excessively high. Generally, the amplitude of the output signal of the transistor of the output buffer is lower than the voltage at the inside of large-scale integration (LSI) which perform at high speed and reduce noise. For example, in a logic such as GTL or the like, while the voltage at inside of LSI is about 3.3 V, 2.5 V or 1.8 V, the amplitude of the output signal from the NMOS transistor is about 0.3 through 0.4 V on the low level side and about 1.2 through 1.5 V on the high level side. That is, a signal which has a higher potential level than potential of a drain terminal, which is an output terminal, is applied on the gate electrode of the transistor. When the voltage of the drain terminal is at a low level, since drain-source voltage Vds of NMOS transistor
430
is small, the drain current of NMOS transistor
430
does not flow immediately, even if a chance in a signal inputted to gate terminal
4301
transits from a high level to a low level. After some time elapses, because the potential of a signal inputted to gate terminal
4301
has started to fall, the drain current of NMOS transistor
430
starts to flow based on the gate voltage, and the level of output terminal
431
rises. Therefore, when the slew rate is slow, the falling of the potential of a signal inputted to the gate terminal is delayed and accordingly, the rise of the output terminal
431
is delayed.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an output buffer circuit in which the start of operation of an output transistor does not change when slew rates are large or small.
Another object of the present invention is to provide an output buffer circuit in which start of change of an output signal does not change when slew rate are large or small. More specifically, there is provided an output buffer circuit in which the start of change of the output signal is not delayed when the slew rate is small.
According to one aspect of the present invention, an output buffer circuit is provide which includes: a first circuit which inputs an input signal and produces a first signal by adjusting the slew rate of the input signal; a second circuit which inputs the first signal and produces a second signal by increasing the slew rate of the first signal until a predetermined time period passes from when the state of the first signal changes; and a transistor which includes a control terminal which inputs the second signal and a terminal connected to a transfer path.
According to another aspect of the present invention, an output buffer circuit is provided which includes: a first circuit which inputs an input signal and produces a first signal by adjusting the slew rate of the input signal; a first transistor which includes a control terminal which inputs the input signal, a first terminal connected to a first power supply terminal and a second terminal; a first delay element which includes an input terminal which inputs the input signal and an output terminal which delays the input signal and outputs a first delayed signal; a second transistor which includes a control terminal which inputs the first delayed signal, a first terminal connected to the second terminal of the first transistor and a second terminal connected to an output terminal of the first circuit; a third transistor which includes a control terminal which inputs the input signal, a first terminal connected to a second power supply terminal and a second terminal; a second delay element which includes an input terminal which inputs the input signal and an output terminal which delays the input signal and outputs a second delayed signal; a fourth transistor which includes a control terminal which inputs the second delayed signal, a first terminal connected to the second terminal of the third transistor and a second terminal connected to the output terminal of the first circuit; and an output transistor which includes a control terminal which is connected to the output terminal of the first circuit and a terminal connected to a transfer path.
According to another aspect of the present invention, an output buffer circuit is provided which includes: a first circuit which inputs an input signal and produces a first signal by adjusting a slew rate of the input signal; a first transistor which includes a control terminal which inputs the input signal, a first terminal connected to a first power supply terminal and a second terminal; a first comparing element which compares an output from the slew rate adjusting circuit with a first potential; a second transistor which includes a control terminal which inputs an output from the first comparing element, a first terminal connected to the second terminal of the first transistor and a second terminal connected to an output terminal of the first circuit; a third transistor which includes a control terminal which inputs the input signal, a first terminal connected to a second power supply terminal and a second terminal; a second comparing element which compares the output from the first circuit (a potential of the first signal) with a second potential; a fourth transistor which includes a control terminal which inputs an output from the second
Lam Tuan T.
NEC Corporation
Sughrue Mion Zinn Macpeak & Seas, PLLC
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