Output buffer circuit

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307475, H03K 1716

Patent

active

051051028

ABSTRACT:
An output buffer circuit which supplies at an emitter coupled logic (ECL) level logic signals from a logic circuit in an integrated circuit realized by a CMOS process. The logic signals are supplied to the gate electrodes of a first P-channel CMOS transistor and a first N-channel CMOS transistor connected in series. A second P-channel CMOS transistor for amplifying the output signal has an open drain configuration. Between the output terminal of the output from the P-channel CMOS transistor of open drain configuration and an external power supply terminal is connected a first resistor. Voltage regulating means, connected between the output terminal and the external power supply terminal, regulates the output voltage at the output terminal. In the voltage regulating means, a voltage setting circuit produces a desired voltage from a voltage supplied from the external power supply terminal. A control voltage generating circuit so generates a control voltage as to have the voltage at the output terminal regulated by the desired voltage on the basis of the voltage produced by the voltage setting circuit. A regulating driver circuit regulates the voltage at the output terminal to a prescribed voltage with the control voltage.

REFERENCES:
patent: 5043604 (1991-08-01), Komaki
patent: 5043607 (1991-08-01), Danckaert et al.

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