Output buffer circuit

Details Output buffer circuit Output buffer circuit

1999-04-20

2000-09-05

Nuton, My-Trang

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

H03B 100, H03K 300

Patent

active

061148865

ABSTRACT:
A preset signal generation circuit comprises a transfer gate for transferring a previously sensed data according to a delayed preset enable signal before the preset signal generation circuit is enabled; delay means for outputting a delayed preset enable signal by delaying a preset enable signal; latch means for storing an output signal of the transfer gate; a first logic element for combining an inverted signal of the delayed preset enable signal and an inverted output signal of the latch means; a first drive means for outputting a source voltage or a ground voltage according to an output signal of the first logic element; a first preset signal control means for controlling an output of the first drive means by having as inputs the preset enable signal and the previously sensed data; a second logic element for combining the delayed preset enable signal and an inverted output signal of the latch means; a second drive means for outputting the source voltage or ground voltage according to an output of the second logic element; and a second preset signal control means for controlling an output of the second drive means by having as inputs the preset enable signal and the previously sensed data.

REFERENCES:
patent: 5638326 (1997-06-01), Hollmer et al.
patent: 5719807 (1998-02-01), Sali et al.
patent: 5723992 (1998-03-01), Yin et al.
patent: 5831458 (1998-11-01), Nakagawa
patent: 5877638 (1999-03-01), Lin
patent: 5926056 (1999-07-01), Morris et al.
patent: 5929668 (1999-07-01), Kim

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