Output buffer arrangement for reducing chip noise without speed

Details Output buffer arrangement for reducing chip noise without speed Output buffer arrangement for reducing chip noise without speed

1988-02-29

1989-08-15

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307448, 3072961, 3072968, 307443, H03K 19017, H03K 19094, H03K 301

Patent

active

048577707

ABSTRACT:
An output buffer arrangement includes a first stable, controlled current source (MO1), a first bidirectional-switching device (24) including a CMOS transmission gate and being responsive to the first current source (MO1) for charging the gate of a pull-up transistor (MO5), a second stable, controlled current source (MO6), and a second bidirectional-switching device (27) including a second CMOS transmission gate and being responsive to the second current source (MO6) for charging the gate of a pull-down transistor (MO10). The output buffer arrangement reduces induced chip noise at low temperature, high power supply voltage without degrading substantially its high operational speed.

REFERENCES:
patent: 4301380 (1981-11-01), Thomas

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