Output address decoder with gating logic for increased speed and

Details Output address decoder with gating logic for increased speed and Output address decoder with gating logic for increased speed and

1977-06-16

1978-07-25

Konick, Bernard

Static information storage and retrieval

Addressing

Using selective matrix

307238, 307243, 307DIG5, 328119, 328154, 340147T, G11C 802

Patent

active

041033493

ABSTRACT:
A Y address decoder used in conjunction with an X-Y matrix array, high density read-only memory unit, that reduces the number of series FET stages in the electrical path needed to evaluate the logic state of an addressed cell location of such a read-only memory unit. The reduction is achieved by gating logic in which the signal stored in the evaluated cell location, is derived from the output terminals of a tier of decoders, the appropriate decoder being connected directly to an output driver by a gate-controlled switch. The gate signal to render each such switch conductive is generated by an AND-OR circuit in repsonse to a unique Y address code, thereby obviating the otherwise time-consuming requirement for the evaluation signal to flow through additional tiers of decoders.

REFERENCES:
patent: 3551900 (1970-12-01), Annis
patent: 3721964 (1973-03-01), Barret et al.
patent: 3757310 (1973-09-01), Croxon
patent: 3774171 (1973-11-01), Regitz
patent: 4006470 (1977-02-01), Mitarai

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