Computer graphics processing and selective visual display system – Display driving control circuitry – Adjusting display pixel size or pixels per given area
Reexamination Certificate
2000-07-28
2004-07-27
Bella, Matthew C. (Department: 2672)
Computer graphics processing and selective visual display system
Display driving control circuitry
Adjusting display pixel size or pixels per given area
Reexamination Certificate
active
06768498
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a monitor and more particularly, to an out of range image displaying device and method of a monitor.
2. Background of the Related Art
A monitor typically executes a series of signal processing operations, such as digital sampling, scaling, and the like for image signals of a predetermined format transmitted from a source, such as a video card of a personal computer connected to the monitor. The monitor then displays the processed image signals on a screen.
Large display devices are presently under development using current technology. Accordingly, the monitor has progressed from a small monitor using a cathode-ray tube into a digital system using a liquid crystal display (LCD) as a representative flat display device adequate to the large monitor.
The image display performance of the monitor is determined by its resolution, which is divided into SVGA (800×600), XGA (1024×768) and SXGA (1280×1024).
As shown in
FIG. 1
, an image processing device of a monitor in the related art includes an A/D converter
1
for converting analog R, G, and B image signals transmitted from a video card into 8-bit digital R, G, and B image signals according to a predetermined sampling clock, which is synchronous with a horizontal synchronizing signal H-sync controlled by a control signal of a microcomputer
4
. A buffer
2
is further provided for temporarily storing the digital R, G, and B image signals in a frame unit, and a video scaler
3
converts the digital R, G, and B image signals outputted from the A/D converter
1
into the signals in a frame unit, which can be displayed on an LCD module. The converted image signals are stored in the frame buffer
2
and transmitted so as to match an input timing signal of the LCD module. Finally, microcomputer
4
recognizes an input image format in accordance with horizontal and vertical synchronizing signals H-sync and V-sync transmitted from the video card, and outputs the control signal to both the A/D converter
1
and the video scaler
3
, so as to match the display with the corresponding format.
In operation, if the analog R, G, and B image signals and the horizontal and vertical synchronizing signals are inputted from the video card, the microcomputer
4
first recognizes the resolution of the inputted image signals, namely, SVGA, XGA and SXGA by using the horizontal/vertical synchronizing signals.
Then, the microcomputer
4
applies the control signal to set the sampling clock of the A/D converter
1
for the digital conversion. The sampling clock is set to correspond to the resolution set by a user, in case where the resolution of the input image signals is below the resolution supported in the monitor, for example, when the resolution of the monitor is XGA (1024×768) and the resolution of the input image signals is XGA or VGA.
In response to the control signal, the A/D converter
1
generates the sampling clock of 95 MHz to sample the XGA image signals to match with the horizontal synchronizing signal timing. It also executes the digital sampling for the input image signals, and outputs the 8-bit digital R, G, and B image signals. At the same time, the A/D converter
1
outputs a dot clock Dot Clock for recognizing the signal of the video scaler
3
.
The video scaler
3
then stores the output of the A/D converter
1
in a frame unit, matching the resolution of XGA in the frame buffer
2
, and outputs the stored output to the LCD module, in accordance with the control signal of the microcomputer
4
.
The LCD module recognizes the 8-bit digital R, G, and B image signals outputted from the video scaler
3
according to a data enable signal D/E and an external clock OUT CLK, and displays the image signals to corresponding to the horizontal/vertical synchronizing signals.
When, however, the resolution of the monitor is XGA and the resolution of the input image signals is SXGA thus exceeding the display performance of the monitor, a sampling clock rate of 135 MHz is required to convert the SXGA image signals into the digital signals.
When the monitor has a resolution of XGA, it can only generate a maximum sampling clock rate of 100 MHz. It thus fails to display the input image signals on the screen, and instead displays the “out of range” on screen display (OSD).
Since the related art monitor cannot display the input image when the input image signals are out of range of the monitor, a problem arises in that the monitor should be replaced by a new monitor that supports the input image mode in order for a user to view the corresponding image.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
SUMMARY OF THE INVENTION
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
Another object of the present invention to provide an out of range image displaying device and method of a monitor capable of achieving a normal display even when the resolution of input image signals exceeds the resolution supported in the monitor.
Another object of the present invention is to provide a device and method of displaying video data having a first format on a monitor having a second format.
To achieve these objects and other advantages in whole or in parts, there is provided an out of range image displaying device of a monitor, which includes an A/D converter for converting analog image signals into digital image signals composed of even pixels, odd pixels, and even/odd pixels in accordance with a sampling clock set by a control signal; a delayer for delaying a horizontal synchronizing signal for a predetermined time; a switch for selecting one of the horizontal synchronizing signal delayed for the predetermined time by the delayer and a normal horizontal synchronizing signal to generate the sampling clock of the A/D converter in accordance with a switching signal; a memory for temporarily storing the digital image signals in a frame unit; a video scaler for storing the even and odd pixels digital image signals outputted from the A/D converter in the memory to thereby build one frame and transmitting the stored output to match with a signal input timing of a display module; and a microcomputer for outputting the switching signal to switch the switch in synchronism with the vertical synchronizing signal, if the resolution of the input image is over the resolution supported in the monitor and at the same time outputting the control signal for setting the sampling clock of the A/D converter to half a normal sampling clock.
To achieve these objects and other advantages in whole or in parts, there is further provided an out of range image displaying method of a monitor, which includes determining whether the resolution of external input image signals is out of range of the monitor; if the resolution of external input image is out of range of the monitor, sampling even or odd pixels for each of the image signals inputted before and after the input of a vertical synchronizing signal; and building each frame with the even and odd pixels sampled in the image signals inputted before and after the input of the vertical synchronizing signal and displaying the frame.
To further achieve the above-described objects of the present invention in a whole or in parts, there is provided an image displaying device that includes an A/D converter to convert image signals of a first format into image signals of a second format, a pixel switch that divides the digital image signal into a plurality of first pixels and a plurality of second pixels, a delay circuit to delay a horizontal synchronizing signal for a prescribed period of time, a switch to select one of the horizontal synchronizing signal and a delayed horizontal synchronizing signal in accordance with a switching signal, a video scaler building a frame from at least one of the first and second pixels of th
Bella Matthew C.
Cunningham G. F.
Fleshner & Kim LLP
LG Electronics Inc.
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