Out of cycle error correction apparatus

Details Out of cycle error correction apparatus Out of cycle error correction apparatus

1981-09-21

1983-10-18

Malzahn, David H.

Excavating

364900, G06F 1108

Patent

active

044109881

ABSTRACT:
This relates to an apparatus and method for providing an accurate data group to the instruction buffer of a data processing system.
The data group is simultaneously applied to the instruction buffer and to the error correcting apparatus. After analysis of the data group in the error correcting apparatus, the operation in progress is aborted if an error has been detected and the error is not correctable. If correctable, the correct instruction data group is applied to the execution unit. If no error is detected in the data group, utilization of the data group proceeds uninterrupted.
Two, three state busses are employed. The first, three-state data bus is used to transmit memory data to the error detection and correction (EDAC) circuitry and to the data output circuits and to transmit input data to the memory. The second three state data transmits data to the instruction buffer, to the EDAC circuitry and also transmits corrected data from the data output circuits to the instruction buffer.

REFERENCES:
patent: 3693153 (1972-09-01), Rosenfeld
patent: 4037091 (1977-07-01), Beuscher
patent: 4058851 (1977-11-01), Scheuneman
patent: 4112502 (1978-09-01), Scheuneman

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