Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
2001-02-28
2003-08-19
Nuton, My-Trang (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C327S109000, C326S086000, C326S087000
Reexamination Certificate
active
06608505
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an output buffer circuit for semiconductor integrated circuits.
2. Prior Art
In general, an LSI (Large Scale Integrated Circuit) has a large load connected to an output terminal thereof. Therefore, in order to drive such a large load, an output buffer circuit having a large drive power is usually provided in the output block of the LSI.
FIG. 1
shows the construction of a conventional output buffer circuit.
As shown in the figure, the output buffer circuit is comprised of a two-input NAND gate NAN
1
, an inverter IN
1
, a two-input NOR gate NOR
1
, a P-channel MOS transistor MP
1
, and an N-channel MOS transistor MN
1
.
The P-channel MOS transistor MP
1
and the N-channel MOS transistor MN
1
provide a sufficient drive power for driving an external load.
In the output buffer circuit constructed as above, if an input signal i changes from a low level to a high level when an enable signal en is at a low level, an output signal na
1
from the two-input NAND gate NAN
1
changes from a high level to a low level, and an output signal nr
1
from the two-input NOR gate NOR
1
also changes from a high level to a low level. Accordingly, the P-channel MOS transistor MP
1
is switched from an OFF-state to an ON-state, while the N-channel MOS transistor MN
1
is switched from the ON-state to the OFF-state. As a result, an output signal x changes from a low level to a high level.
During this transition of the output signal from the low level to the high level, there occurs a time period when the P-channel MOS transistor MP
1
and the N-channel MOS transistor MN
1
are both held in the ON-state simultaneously. During this time period, a large current (through current) flows between a power supply VDD and ground GND, which generates noise on the power line and the ground line, and can lead to erroneous operation of the LSI.
The above problem will be described more in detail with reference to FIG.
2
.
FIG. 2
shows the P-channel MOS transistor MP
1
and the N-channel MOS transistor MN
1
each having an inductance L connected thereto.
These inductances L are parasitic inductances interposed, respectively, between the power supply VDD outside the LSI and the source of the MOS transistor MP
1
inside the LSI and between the ground GDN outside the LSI and the source of the MOS transistor MN
1
inside the LSI. When the through current i flows between the P-channel MOS transistor MP
1
and the N-channel MOS transistor MN
1
each connected to the corresponding inductance L, a spike noise is generated across each of the inductances L.
The noise level of the spike noise can be expressed in terms of a spike voltage (&Dgr;V) by the following equation (1):
&Dgr;V=−L·di/dt
(1)
In the output buffer circuit, since the P-channel MOS transistor MP
1
and the N-channel MOS transistor MN
1
each have a large load-driving power, a large through current i flows between them, which generates a large spike noise.
The generation of the big spike noise leads to erroneous operations of other circuits within the LSI.
Further, the
FIG. 1
output buffer circuit suffers from a problem that the through current causes an increased current consumed by the buffer circuit.
An output buffer circuit intended for preventing generation of the through current and noise described above has been proposed e.g. by Japanese Laid-Open Patent Publication (Kokai) No. 05-327444.
FIG. 3
shows the construction of the proposed output buffer circuit.
The output buffer circuit is comprised of an input terminal
1
, an output terminal
2
, a pre-driver
3
, a delay circuit block
4
, and a final driver
5
.
The final driver
5
is comprised of P-channel MOS transistors P
1
, P
2
, and N-channel MOS transistors N
1
, N
2
. The P-channel MOS transistors P
1
, P
2
each have a source thereof connected to a positive power supply VDD, while the N-channel MOS transistors N
1
, N
2
each have a source thereof grounded. The P-channel MOS transistors P
1
, P
2
and the N-channel MOS transistors N
1
, N
2
each have a drain thereof connected to the output terminal
2
.
The delay circuit block
4
is interposed between the input terminal
1
and the final driver
5
and composed of a delay block
6
, a two-input NAND gate
11
, and a two-input NOR gate
12
. The delay block
6
delays an input signal thereto by a predetermined delay amount td. An output signal from the delay block
6
is delivered to one of the input terminals of the two-input NAND gate
11
and one of the input terminals of the two-input NOR gate
12
. The other input terminal of the two-input NAND gate
11
and that of the two-input NOR gate
12
are each supplied with an input signal i. The two-input NAND gate
11
supplies an output signal to the gate of the P-channel MOS transistor P
2
of the final driver
5
, while the two-input NOR gate
12
supplies an output signal to the gate of the N-channel MOS transistor N
2
of the same.
The pre-driver
3
is interposed between the input terminal
1
and the final driver
5
. The pre-driver
3
delivers a signal formed by inverting the polarity of the input signal i to the respective gates of the P-channel and N-channel MOS transistors P
1
and N
1
of the final driver
5
.
Next, the operation of the above output buffer circuit will be described with reference to
FIGS. 4A
to
4
J.
FIGS. 4A
to
4
J collectively form a timing chart which is useful in explaining the operation of the
FIG. 3
output buffer circuit.
First, assuming that the input signal i changes from a low level to a high level at a time t
01
, the output signal from the pre-driver
3
changes from a high level to a low level (see
FIGS. 4A
,
4
B). As a result, the P-channel MOS transistor P
1
is switched from the OFF-state to the ON-state, while the N-channel MOS transistors N
1
is switched from the ON-state to the OFF-state (see
FIGS. 4F
,
4
G). Accordingly, an output signal from the final driver starts changing from a low level to a high level (FIG.
4
J).
After the lapse of a delay time td from the time t
01
(i.e. at a time t
02
), the output signal from the delay block
6
changes from a low level to a high level (see FIG.
4
C). At the same time, the output signal from the two-input NAND gate
11
changes from a high level to a low level (see FIG.
4
E), whereby the P-channel MOS transistor P
2
is switched from the OFF-state to the ON-state (see FIG.
4
H).
Consequently, the P-channel MOS transistors P
1
and P
2
perform additional driving operation to cause an output signal level to rise sharply.
In the output buffer circuit described above, between the time t
01
at which the input signal i changes and the time t
02
after the lapse of the delay time td from the time t
01
, there exists no time period over which the P-channel MOS transistor P
2
and the N-channel MOS transistor N
2
are both held in the ON-state simultaneously (see
FIGS. 4H
,
4
I), which prevents a through current from flowing between the two transistors P
2
and N
2
.
However, when a large capacity load connected to the output buffer circuit is to be charged or discharged, a large drive power is required upon switching between the charge and the discharge. In the above output buffer circuit, when the input signal i changes from the low level to the high level, one of the P-channel MOS transistors parallel-connected to the load, i.e. the P-channel MOS transistor P
1
, is switched from the OFF-state to the ON-state (see FIG.
4
F), while the P-channel MOS transistor P
2
is switched from the OFF-state to the ON-state after the lapse of the delay time td (see FIG.
4
H).
That is, immediately after the input signal i changes as described above, the P-channel MOS transistor P
1
alone can provide a drive power. Therefore, it is impossible to obtain a sufficient drive power for charging or discharging the large capacity load, which results in delayed response.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an output buffer circuit which is capable of obtaining a
Nguyen Hiep
Nuton My-Trang
Pillsbury & Winthrop LLP
Yamaha Corporation
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