Oscillator runaway detect and reset circuit for PLL clock genera

Details Oscillator runaway detect and reset circuit for PLL clock genera Oscillator runaway detect and reset circuit for PLL clock genera

1996-08-26

1999-01-26

Chung, Phung M.

Excavating

371 48, 371 471, G06F 1100

Patent

active

058645721

ABSTRACT:
An oscillator runaway detection circuit is provided with a synchronous delay line such that energy saving or sleep modes of operation are not mischaracterized as oscillator runaway. A Schmitt trigger monitors oscillator control voltage at a filter capacitor. If the control voltage is below a predetermined limit, indicating a possible runaway condition, a signal is output to a synchronous delay line. The output of the Schmitt trigger is propagated through the synchronous delay line comprising a plurality of flip-flops clocked by the system reference clock. The output of the synchronous delay line drives a transistor which in turn may charge the filter capacitor to reduce the control voltage and thus lower the frequency of the oscillator. A one-shot coupled to the clock tree monitors for clock activity in the clock tree. If clock activity is present, it is presumed that a runaway condition does not exist, and the output of the one-shot resets the flip-flops in the delay line, preventing the output of the Schmitt trigger to charge/reset the oscillator.

REFERENCES:
patent: 5220293 (1993-06-01), Rogers
patent: 5371425 (1994-12-01), Rogers

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