Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1997-12-10
2002-03-19
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S189090, C365S233100
Reexamination Certificate
active
06359809
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to providing a low frequency oscillator and, more particularly, to providing a low power low frequency oscillator for enabling voltage regulation circuitry in memory arrays.
BACKGROUND OF THE INVENTION
Many computing systems such as personal computers, automotive and airplane control, cellular phones, digital cameras, and handheld communication devices use nonvolatile writeable memories to store either data, or code, or both. Such nonvolatile writeable memories include Electrically Erasable Programmable Read-Only Memories (EEPROMs) and flash Erasable and Electrically Programmable Read-Only Memories (flash EPROMs, or flash memories). Nonvolatility is advantageous for allowing the computing system to retain its data and code when power is removed from the computing system. Thus, if the system is turned off or if there is a power failure, there is no loss of code or data.
Nonvolatile semiconductor memory devices are fundamental building blocks in prior art computer system designs. The primary mechanism by which data is stored in nonvolatile memory is the memory cell. One type of prior nonvolatile semiconductor memory is the flash electrically-erasable programmable read-only memory (flash EEPROM). Prior art flash EEPROMs typically allow for the simultaneous reading of several flash cells. Further, typical prior art flash EEPROMs have a storage capacity that is much greater than the amount of data that can be output at any one time. Accordingly, each output of a flash EEPROM is typically associated with an array of flash cells that is arranged into rows and columns, where each flash cell in an array is uniquely addressable. When a user provides an address, row and column decoding logic in the flash EEPROM selects the corresponding flash cell.
Many electronic systems that take advantage of flash memories are small portable devices that rely on resident batteries for power. Consequently, it is advantageous to reduce the power consumption of these devices in order to increase the length of time between battery chargings. Furthermore, it is advantageous to reduce the size of the internal circuitry of these devices so as to make the portable devices as small in size and light in weight as possible. The power consumption is reduced in many portable electronic devices by operating specific components in a lower power standby mode during periods when these components are not required. Typically, this low power standby mode will reduce the overall current consumed by the component or circuit.
FIG. 1
is a typical prior art flash memory circuit
100
used in a low power standby mode. The positive charge pump
102
provides a regulated voltage of approximately five volts over decoder supply line
106
to the X-decoder
110
of the memory array
112
. The negative charge pump
104
provides a voltage of approximately negative five volts over decoder supply line
108
to the X-decoder
110
of the memory array
112
. The wordline voltages should be controlled during read operations in multiple level cell flash memories in order to reliably interpret the states. Therefore, in a standby mode, this circuit should maintain these wordline voltages and a reference voltage source
116
while minimizing the current drawn by the circuit. Maintaining these wordline voltages requires current, however, because the junctions and diffusions on the nodes of the positive pump
102
, the negative pump
104
, and the voltage reference
116
result in a current leakage while the circuit is in the standby mode. The most power efficient method of accommodating this leakage current is to periodically pulse, or refresh, the positive pump
102
, the negative pump
104
, and the voltage reference
116
using an oscillator
114
.
A problem with the typical prior art flash memory circuit
100
is that the leakage current is not the same for the voltage reference
116
, the positive pump
102
, and the negative pump
104
. Typically, the positive pump
102
touches more diffusion resulting in more leakage, so the positive pump
102
has the highest refresh rate, approximately 100 microseconds. The voltage reference has a refresh rate of approximately 1 millisecond. The negative pump
104
has the slowest refresh rate, approximately 10 milliseconds. Because a typical prior art oscillator only outputs one clock signal, these different refresh rates among components result in the oscillator pulsing at a frequency that is the highest of the frequencies required by any of these components. Thus, as the oscillator pulses at a higher frequency to accommodate the refresh rate of the positive pump
102
, the current draw is higher because the negative pump
104
and the voltage reference
116
are being turned on, and drawing current, when they are not required to be turned on. Furthermore, the prior art oscillator design consumes a significant amount of silicon area. Consequently, a low frequency oscillator is needed that periodically enables multiple voltage regulation circuitry components by generating a wide range of multiple low frequency clock signals, the low frequency resulting in lower standby current, while requiring less silicon area than typical prior art designs.
SUMMARY OF THE INVENTION
A low frequency oscillator is described. The low frequency oscillator has a bias circuit including a metal-oxide semiconductor (MOS) resistor. A biased ring oscillator is coupled to the bias circuit. The biased ring oscillator includes multiple current limiting transistors.
Other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description and appended claims that follow below.
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Evertt Jeffrey J.
Tedrow Kerry D.
Blakely , Sokoloff, Taylor & Zafman LLP
Le Vu A.
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