Oscillator for measuring on-chip delays

Horology: time measuring systems or devices – Time interval – Electrical or electromechanical

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324 731, 324763, 324765, 327265, 331 55, 331 57, 714733, G04F 800, G04F 1000, G01R 3102, G01R 3128, H03B 2700

Patent

active

061341916

ABSTRACT:
A circuit separately measures one or both of the rising-edge and falling-edge signal propagation delays through a signal path of interest. The greater of these delays can then be used to establish a worst-case delay for the signal path. The worst-case delay can be used, in turn, to create accurate timing specifications for logic circuits that include similar or identical signal paths. To determine the delay through the signal path, the signal path is used with a second, typically identical, signal path to create alternating feedback paths of an oscillator. The oscillator is configured to output a test-clock signal having a period proportional to either the rising- or falling-edge delays through the two signal paths. The test-signal transitions are counted over a predetermined time period to establish the average period of the oscillator. Finally, the average period of the oscillator is related to the average signal propagation delay through the signal path of interest.

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"Signal Delay in RC Tree Networks," IEEE Transactions on Computer-Aided Design, vol. CAD-2, No. 3, Jul. 1983, pp. 202-211.
"The Programmable Logic Data Book", 1998, available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124, pp. 4-5 to 4-40.

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