Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2001-05-01
2002-05-14
Wambach, Margaret R. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S170000, C327S536000
Reexamination Certificate
active
06388481
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to phase lock loop circuits, and in particular, circuitry within the feedback loop for controlling the oscillator and minimizing phase noise and spurious signal content.
2. Description of the Related Art
Referring to
FIG. 1
, a typical conventional phase lock loop circuit
10
includes an oscillator
12
(typically a voltage-controlled oscillator, or VCO) which is driven by a control signal
25
to produce its oscillator output signal
13
. This output signal
13
is fed back to a prescaler
14
which divides down the frequency of this signal
13
. The reduced frequency signal
15
is then further divided down by a counter
16
having a programmable divisor N. The final frequency-divided signal
17
is provided to a phase detector
20
.
A reference signal
11
provided by an external reference oscillator (not shown) is divided down in frequency by another counter
18
having another programmable divisor R. The resultant frequency-divided signal
19
is also provided to the phase detector
20
. The phase detector
20
compares the relative phases of these two signals
17
,
19
, using the frequency-divided reference signal
19
as the “target” with respect to the desired phase of the feedback signal
17
. (This phase comparison is done in accordance with well-known conventional techniques and hence need not be described further here.) Based upon this phase comparison, the phase detector provides two phase signals
21
u
,
21
d
. One of the signals
21
u
is asserted when it is necessary to increase the frequency of the feedback signal
17
in order to have its phase match that of the reference signal
19
. The other signal
21
d
is asserted when it is necessary for the frequency of the feedback signal
17
to be decreased in frequency so as to have its signal phase match that of the reference signal
19
.
These two phase signals
21
u
,
21
d
are provided to a charge pump circuit
22
(discussed in more detail below) which provides an output current signal
23
i
and a feedback signal
23
f
. The output current signal
23
i
is used to “pump up” or “pump down” the electrical charge stored by a capacitor (not shown) within the loop filter circuit
24
in accordance with well known conventional techniques. As a result of this stored electrical charge, the loop filter
24
provides the control signal
25
for the oscillator
12
. The feedback signal
23
f
is used to control the assertion and deassertion of the phase signals
21
u
,
21
d
generated by the phase detector
20
.
Referring to
FIG. 2
, a conventional embodiment
22
a
of the charge pump
22
(FIG.
1
), includes an input buffer
102
u
/
102
d
, such as an inverter, a bias circuit
104
u
/
104
d
and a current source circuit
106
u
/
106
d
for each of the “pump up” and “pump down” signal channels. For each channel, the incoming signal
21
is buffered and inverted by the inverter
102
u
/
102
d
. The resulting inverted input signal
103
u
/
103
d
drives the bias circuit
104
u
/
104
d
and the current source circuit
106
u
/
106
d
. Assertion of this signal
103
u
/
103
d
causes the bias circuit
104
u
/
104
d
to generate a bias signal
105
u
/
105
d
. Coincident assertions of this inverted input signal
103
u
/
103
d
and bias signal
105
u
/
105
d
cause the current source circuit
106
u
/
106
d
to generate its output current
107
u
/
107
d
. For the “pump up” channel, the output signal
107
u
is a source current, while for the “pump down” channel, the output current
107
d
is a sink current. These source
107
u
and sink
107
d
currents sum at the output note
108
to produce the net, or composite, output current
23
i.
Referring to
FIG. 3
(in conjunction with FIG.
2
), it can be seen that during a charge pump event (either pump up or pump down) the bias
104
u
/
104
d
and current source (or sink)
106
u
/
106
d
circuitry are both enabled by their corresponding phase signal
21
and bias signal
105
u
/
105
d
. However, the bias circuitry
104
u
/
104
d
takes a longer interval of time to become fully enabled, or turned on, than the current source (or sink) circuitry
106
u
/
106
d
. And, since the bias circuitry
104
u
/
104
d
must be turned on before the current source (or sink) circuitry
106
u
/
106
d
can effectively generate its output current
107
u
/
107
d
and thereby provide the appropriate charge to the loop filter
24
(FIG.
1
), the leading and trailing edges of the output current
23
i
waveform are dictated by how fast the bias circuitry
104
u
/
104
d
turns on. Hence, the net output current
23
i
has slow rise and fall times which cause the output current signal
23
i
to have significant low frequency signal components. These low frequency signal components cannot be effectively filtered out by the lowpass loop filter
24
. As a result, these low frequency signal components appear as phase noise or spurious signals within the output signal
13
from the oscillator
12
(FIG.
1
).
As noted above, the feedback signal
23
f
determines when the phase signals
21
u
,
21
d
from the phase detector
20
are deasserted. Upon coincident assertion of the output source
107
u
and sink
107
d
currents, the feedback signal
23
f
is asserted, following which the phase signals
21
u
,
21
d
from the phase detector
20
are deasserted. Such coincident assertions of the source
107
u
and sink
107
d
currents are detected by a monitor circuit
110
which monitors these currents (in a conventional manner) to produce the feedback signal
23
f.
Accordingly, it would be desirable to have an oscillator control circuit capable of generating charge pump current signals with significantly reduced low-frequency signal components so as to minimize in-band phase noise and spurious signals associated with such low-frequency signal components.
SUMMARY OF THE INVENTION
An oscillator control circuit for a phase lock loop in accordance with one embodiment of the present invention provides source and sink currents at the output of the charge pump circuitry with high slew rates. The fast rise and fall times of the waveforms for these current signals cause minimal low-frequency signal components to be included in the frequency spectrum of the output signals. Instead, any harmonics or other signal components associated with these waveforms occur at significantly higher frequencies, thereby allowing them to be filtered out by the loop filter before reaching the oscillator. Additionally, these fast rise and fall times for the current signal pulses cause such signal pulses to be of shorter durations, thereby minimizing the amount of spurious signal energy being produced. Furthermore, these fast signal pulse edges translate into a higher effective charge pump output signal relative to the noise, thereby resulting in an increased signal-to-noise ratio (SNR) and hence an improvement in phase noise. Hence, in-band phase noise and spurious signal content are significantly reduced.
An apparatus including oscillator control circuitry for a phase lock loop in accordance with one embodiment of the present invention includes phase detection circuitry, control signal generator circuitry, bias control circuitry and charge pump circuitry. The phase detection circuitry, responsive to a reference signal, an oscillator feedback signal and a charge pump feedback signal, provides first and second phase signals indicative of a phase difference between the reference and oscillator feedback signals with respective assertion states responsive to the phase difference and respective deassertion states responsive to the charge pump feedback signal. The control signal generator circuitry, coupled to the phase detection circuitry and responsive to the first and second phase signals, provides: a first pump control signal with assertion and deassertion states corresponding to and time-delayed from the first phase signal assertion and deassertion states; a first bias control signal with assertion and deassertion states responsive to the first phase signa
Broughton David Lindsay
Huard Jeffrey Mark
Wong Kim Yeow
Dalla Valle Mark A.
National Semiconductor Corporation
Wambach Margaret R.
Wildman Harrold Allen & Dixon
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