Oscillators – Solid state active element oscillator – Transistors
Reexamination Certificate
1999-09-30
2001-05-08
Grimm, Siegfried H. (Department: 2817)
Oscillators
Solid state active element oscillator
Transistors
C331S046000, C331S17700V
Reexamination Certificate
active
06229406
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention pertains to an improved oscillator circuit having increased signal power.
2. Description of the Related Art
Oscillator circuits include a tank section having one or more inductance and capacitance elements which cause signal oscillation. All tank circuits inherently exhibit losses that are caused, for example, by resistance in the inductance elements. Such losses result in attenuation or decay over time of an oscillated output signal. In each oscillator signal cycle, a maximum of the losses coincides with the maximum value of the oscillated output signal, i.e. the maximum amplitude of the oscillated signal. To combat this problem, an active stage is included in oscillator circuits to compensate for signal decay by adding energy to the tank. A problem with such an approach, however, is that the DC power consumed by the circuit is usually much greater than the signal power it produces. And, as discovered by the inventor recently, to produce more signal power from a given amount of DC power, it is necessary to replenish the energy into the tank in as narrow a pulse as possible.
A known and widely used oscillator circuit suffering from the drawbacks discussed above is the Colpitts oscillator
10
shown in
FIG. 1
which provides single-ended oscillation especially when the losses in the tank are large or the quality factor is small. This oscillator includes a tank stage having an inductor L and a capacitor pair C
1
, C
2
, driven by a power replenishing stage having a transistor Q and a DC current source
12
which draws a constant current I. As shown, capacitors C
1
, C
2
are connected at a node N
1
which is located at the source terminal of the transistor Q where a voltage V
1
is present. Capacitor C
1
is connected to inductor L at a node N
2
, at which a voltage V
2
is present. The power supply V, bias voltage V
B
and DC current source
12
provide proper bias condition for the transistor Q. Voltage V
2
represents the oscillated output signal of circuit
10
.
When the tank stage begins to oscillate, the value in signal V
2
increases and decreases periodically around its quiescent point V. The signal V
1
is basically a voltage divided value of signal V
2
between capacitor C
1
and C
2
and thus, also varies around its quiescent point. As signals V
2
and V
1
increase, the transistor Q—which has a turn-on or threshold voltage V
TH
—will be turned off because the voltage between the gate and source terminals (V
gs
) decreases below the value of V
TH
. As a result, and because capacitor C
1
resembles an open-circuit condition for a DC current, the current I required by the current source
12
is provided through the discharge of capacitor C
2
. As oscillation continues, this causes the values of V
1
and V
2
to decrease until the voltage V
gs
exceeds V
TH
. At this point, transistor Q turns on to provide current to current source
12
and to recharge capacitor C
2
. Consequently, the signals V
1
and V
2
increase again.
A drawback of the prior art circuit
10
of
FIG. 1
is that the conduction duration of the transistor is dictated by a single control signal namely, V
1
, which is related to the output signal V
2
through the ratio of C
1
and C
2
. The choice of C
2
thus serves dual diametrically opposing functions. In particular, C
2
needs to be small in order to produce a large variation in signal V
1
to turn the transistor on and off in as short a duration as possible. On the other hand, C
2
needs to be large in order to provide the current drawn by the current source
12
in as long a duration as possible. The limitation on the duration of transistor conduction resulting from this dilemma restricts the capabilities of the prior art circuit for attaining an increased signal power and, consequently, an increased frequency stability.
SUMMARY OF THE INVENTION
An oscillator circuit is provided for attaining increased oscillator signal power and increased frequency stability. The inventive circuit contains a tank stage having an inductor and at least a pair of capacitors for producing an oscillated signal. An active stage is electrically connected to the tank stage for injecting power to the tank stage to compensate for the losses that occur in the tank. The active stage includes a transistor having a gate terminal, a source terminal and a drain terminal. A supply voltage V, a bias voltage V
B
and a DC current source are connected to the active stage to provide a proper bias condition. The capacitors are also connected to the source terminal to provide a first control signal to the source terminal for selectively activating the transistor when a voltage between the gate and source terminals exceeds a threshold voltage value of the transistor. Means for producing a second control signal and for providing the second control signal to the gate terminal is provided for insuring that the transistor can be turned on and off in as short a duration as possible.
In a preferred embodiment, the control means includes a second inductor electromagnetically coupled to the first inductor for producing the second control signal when current flows through the first inductor.
In another preferred embodiment, a differential oscillator circuit is provided that exhibits improved oscillating signal power. The differential circuit includes two circuit branches, with each branch containing a tank stage and an active stage configured in a cross coupled arrangement wherein the oscillating signals produced by each tank stage are provided to the respective gate terminals of the transistors of the other active stage. In this manner, each oscillating signal from each tank stage operates as the second control signal for the transistor in the other stage.
Other objects and features of the present invention will become apparent from the following detailed description considered in conjunction with the accompanying drawings. It is to be understood, however, that the drawings are designed solely for purposes of illustration and not as a definition of the limits of the invention, for which reference should be made to the appended claims.
REFERENCES:
patent: 4419634 (1983-12-01), Druegh et al.
patent: 4454485 (1984-06-01), Fisher
patent: 4596966 (1986-06-01), Derewonko et al.
Agere Systems Inc.
Grimm Siegfried H.
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