Oscillators – Ring oscillators
Reexamination Certificate
1998-09-03
2001-10-16
Pascal, Robert (Department: 2817)
Oscillators
Ring oscillators
C331S066000, C326S095000
Reexamination Certificate
active
06304148
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to an oscillator circuit, specifically, to an oscillator circuit for the purpose of generating a clock signal used in the refresh circuit of a DRAM.
BACKGROUND OF THE INVENTION
A dynamic random-access memory (DRAM), is typically constructed of memory cells comprising one transistor and one capacitor. A larger capacity memory thus can be realized when the memory cell area is reduced in size. Because the storage of data is accomplished by holding a charge on the capacitor, there is the problem that, with the passage of time, the charge held in the capacitor discharges, and the storage data is lost. In order to accurately save the stored data, a DRAM typically includes the so-called refresh operation. The refresh operation performs a rewrite of the data for the memory cells at a fixed time spacing. A self-refresh circuit is typically provided in the ordinary DRAM to control the refresh operation.
FIG. 5
is a schematic showing one construction example of a self-refresh circuit. The self-refresh circuit shown in the figure is constructed by means of the self-refresh oscillator
10
, the counter
20
, the interval time detector
30
, the entry time detector
40
, the mode set/reset control circuit
50
, the internal RAS control circuit
60
, and the internal RAS generator circuit
70
.
The self-refresh circuit is started by means of a control signal CBR. The counter
20
starts the count in response to a clock signal CLK sent from the self-refresh oscillator
10
, and the count value CNT is output to the interval time detector
30
and the entry time detector
40
.
A value corresponding to the desired interval time is set in the interval time detector
30
, and a value corresponding to the desired entry time is set in the entry time detector
40
, respectively. If the value set as the entry time and the counter value CNT match in the entry time detector
40
, a mode set signal MST is output, the refresh mode is set by means of a mode set/reset control signal
50
in response to this, and the mode signal MDST is switched, for example, from a low level to a high level.
By this means, the pulse signal INTRAS for the purpose of the internal refresh is generated by means of the internal RAS generator circuit
70
, and output. At the same time, the counter
20
is reset by means of the internal RAS control signal circuit
60
, and the count is newly begun. When the count value CNT and a value that was set beforehand in the interval time detector
30
match, the control signal IST is output from the interval time detector
30
, and in response to this a pulse signal INTRAS is newly sent by means of the internal RAS generator circuit
70
. Then, the counter
20
is again reset by means of the internal RAS control circuit
60
, and the count is begun. This operation is repeatedly conducted until the control signal CBR is reset, the pulse signal INTRAS is generated by means of the self-refresh circuit, and the refresh of the DRAM is conducted in response to this.
FIG. 6
is a waveform chart showing the operation of the self-refresh circuit. As is illustrated, when the control signal CBR is placed in the active state, for example, in the state of a high level, the self-refresh circuit is started. The counter
20
is started by means of the internal RAS control circuit
60
, and the counter operation by means of the counter
20
is initiated. Also, as for the self-refresh oscillator
10
, when the control signal CBR is set to the high level, its oscillation operation is reset by means of the internal RAS control circuit
60
.
The count value from the counter
20
and the preset value are compared by means of the entry time detector
40
, and if matching, the mode control signal MST is generated, and is output to the mode set/reset control circuit
50
. In response to this, the mode signal MDST is switched from the low level to the high level by means of the mode set/reset control circuit
50
, and the refresh mode is set. The time T
E
from when the control signal CBR is set to the active state until the mode signal MDST is switched to the high level is the entry time, and is controlled by means of the entry time detector
40
.
When it is set to the refresh mode, the first pulse signal INTRAS is generated by means of the internal RAS generator circuit
70
and is output, the counter
20
is reset in response to this, and a new count is begun. When the count value CNT matches the value set beforehand in the interval time detector circuit
30
, the control signal IST is output by means of the interval time detector
30
, and the second pulse signal INTRAS is generated by means of the internal RAS generator circuit
70
in response to this. The counter
20
is again reset in response to this pulse signal INTRAS, and the count is begun.
The spacing T
R
for the second and the first pulse signals INTRAS is controlled by means of the interval time detector
30
. Also, the width T
D
for the pulse signal INTRAS is controlled, for example, by means of the delayed time of the delay circuit provided in the internal RAS generator circuit
70
. In the case of a 64 Mb DRAM, the spacing T
R
for the pulse signal INTRAS is set, for example, to 16 &mgr;s, and the pulse with T
D
of the pulse signal INTRAS, for example, is set to 50-60 ns.
The above-mentioned operation is repeatedly conducted, and the pulse signal INTRAS is repeatedly generated for the cycle T
R
until the control signal CBR is reset to the low level. The time from when the control signal CBR is set, and the initial pulse signals INTRAS is generated, until the final pulse signal INTRAS is ended, is one cycle of the refresh operations. For example, in the case of a 64 Mb DRAM, all of the memory cells are refreshed by means of the pulse signal INTRAS being generated 4096 times. As mentioned above, in the event the cycle T
R
for the pulse signal INTRAS is 16 &mgr;s, one cycle for the refresh becomes (16 &mgr;s×4096 =65.5 ms).
The self-refresh oscillator
10
, for example, is constructed by means of a ring oscillator constructed by means of connecting an odd number of stages of inverters in a ring configuration and a current source that supplies current to the oscillator. One construction example of the current supply circuit is shown in FIG.
7
. FIG.
7
(
a
) is a schematic of the current source circuit
100
, and FIG.
7
(
b
) shows its equivalent circuit.
As is shown in FIG.
7
(
a
), the current source circuit
100
is constructed by means of the pMOS transistors PT
1
, PT
2
, PT
3
, PT
4
, PT
5
, PT
6
, switches SW
1
, SW
2
, SW
3
, SW
4
, SW
5
, and the nMOS transistor NT
1
.
The pMOS transistors PT
1
to PT
6
are connected in series between the power supply voltage VDL and the node ND
1
. The gates of these pMOS transistors are connected to the common potential V
ss
, and their base regions back gates are connected in common to the power supply voltage VDL. Also, the switches SW
1
, SW
2
, SW
3
, SW
4
, SW
5
are respectively connected between the source and drain of the pMOS transistors PT
2
, PT
3
, PT
4
, PT
5
, PT
6
.
The switches SW
1
to SW
5
, for example, are constructed by means of metal switches.
Since the pMOS transistors PT
1
to PT
6
are constructed by linear type regions, the partial circuits constructed by means of these transistors can be considered as being replaced by resistive elements R having prescribed resistance values. By this means, the current source circuit
100
can be simplified by means of the equivalent circuit shown in FIG.
7
(
b
). In other words, the current source circuit
100
can be shown by means of the resistive element R that is connected between the power supply voltage VDL and the node ND
1
, and the nMOS transistor NT
1
that is diode connected. The gate and drain of the nMOS transistor NT
1
are connected in common to the node ND
1
, and the source is connected to the common potential V
ss
. The bias voltage V
BIAS
is output by means of the node ND
1
. Also, the node ND
1
is connected to the gate of each nMOS transistor that suppl
Mimura Akimitsu
Nomura Masayoshi
Takahashi Tsugio
Yokoyama Yuji
Glenn Kimberly E
Pascal Robert
Peterson Bret J.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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