Oscillators – Automatic frequency stabilization using a phase or frequency... – Tuning compensation
Reexamination Certificate
2000-09-27
2002-01-08
Grimm, Siegfried H. (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Tuning compensation
C331S025000, C331S03600C, C331S044000, C331S074000, C331S158000, C331S17700V, C331S17700V, C331S179000
Reexamination Certificate
active
06337600
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an oscillator used as a clock source oscillation circuit for an information processor or a communication processor and capable of supplying a signal used as a reference for desired frequencies.
2. Description of Related Art
For use in information processors such as computers or in communication apparatuses, an oscillator in which a piezoelectric resonator such as a quartz resonator is used as an oscillation source has been used as a clock source or the like. Each of processing sections forming an information processor is supplied with a clock signal or the like having a suitable frequency on the basis of a signal supplied from such an oscillator.
FIG. 18
shows an example of a conventional oscillator using a PLL circuit. This oscillator
90
is arranged so as to be able to select one of a plurality of frequencies predetermined to be output, and to output a signal having the selected frequency. The oscillator
90
has a quartz resonator
1
, an oscillation signal output section
10
which oscillates the quartz resonator
1
to output an oscillation signal &phgr;
1
having a resonant frequency fc of the quartz resonator
1
, a programmable divider (reference divider: RD)
15
which divides (by M) the oscillation signal &phgr;
1
to generate a reference signal &phgr;
2
having a frequency fr, a PLL circuit
20
which operates by being supplied with this reference signal &phgr;
2
, a programmable divider (output divider: OD)
30
which divides (by X) a multiplied signal &phgr;
3
output from the PLL circuit
20
and having a frequency fp to generate an output signal &phgr;
4
having a frequency fo, and a buffer
35
which amplifies and outputs the output signal &phgr;
4
. The PLL circuit
20
has a phase comparator
21
which compares the phase of reference signal &phgr;
2
supplied from the RD
15
and the phase of a signal fed back from a voltage controlled oscillator (VCO)
23
, a low-pass filter (LPF)
22
which cuts off high frequency components of an output of the phase comparator
21
and supplies the cut output to the VCO
23
, and the VCO
23
that oscillates so that the phases of the two signals input to the phase comparator
21
coincide with each other. Further, a feedback divider (FD)
24
is provided in a feedback circuit of the PLL circuit. The frequency of an output of the VCO
23
is divided (by N) by the FD
24
to be fed back to the phase comparator
21
. Consequently, in the PLL circuit
20
, multiplied signal &phgr;
3
formed by multiplying the signal input to the phase comparator
21
by N is output from the VCO
23
.
Each of the dividers (frequency dividers)
15
,
24
, and
30
used in this oscillator
90
is a programmable divider capable of dividing the frequency of the input signal by a set frequency dividing number. Accordingly, in the oscillator
90
shown in
FIG. 18
, combinations of frequency dividing numbers M, N, and X for the frequencies to be output are previously set in a memory
95
, and one of the combinations of the frequency dividing numbers M, N, and X stored in the memory
95
can be selected by a decoder
96
connected to an external input
94
. For example, if the oscillator
90
uses a quartz resonator
1
having a resonant frequency fc of 20 MHz, it can select and output one of sixteen different frequencies according to a combination of four external terminals S
0
, S
1
, S
2
, and S
3
.
Use of a PLL oscillator using such a programmable divider has enabled one oscillator to cover a plurality of frequencies, thus making it possible to provide an oscillator capable of operating as stably as conventional quartz oscillators in the period before a restricted appointed limit of delivery. Recently, however, various requirements have been posed for reference oscillation sources and there has been a need to prepare various types of oscillators even if the above-described PLL oscillator is used. Further, the speed of development of information processors or communication apparatuses have been remarkably accelerated and, therefore, a need for manufacturing oscillators of new specifications or frequencies in a short period has arisen. On the other hand, the operating accuracies of information processors and communication apparatuses have been improved, so that there is a need to also improve the frequency accuracy of signals output from oscillators.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an oscillator which is capable of outputting an output signal that is stable and accurate in frequency in comparison with conventional PLL oscillators, which can be manufactured in a short period, and which can be supplied at a low cost.
In the conventional PLL circuit, as described above, a quartz resonator having a resonant frequency adjusted with a predetermined degree of accuracy is used and the resonant frequency is multiplied by a predetermined combination of frequency dividing numbers to obtain an output signal of an intended frequency. On the other hand, the inventors of the present invention have found that output signals of various frequencies required by users can be obtained by setting the frequency dividing numbers for dividers to suitable values independent of each other. That is, in an oscillator of the present invention, an output signal of a desired frequency can be obtained by enabling suitable setting of frequency dividing numbers for dividers even if the resonant frequency of a quartz resonator is not adjusted to an ideal value, and high-precision output signals adjusted to various frequencies required by users can be obtained regardless of whether or not they are to be output.
This will be described in more detail with reference to a model case shown in FIG.
1
. In
FIG. 1
, frequencies fp of an output signal (multiplied signal) from a PLL circuit are plotted, frequencies fp being obtained by changing the value of frequency dividing number M for a reference divider RD step by step from 5 to 10 and by changing the value of frequency dividing number N for the FD of the PLL step by step between 1 to 30 with respect to each value of frequency dividing number M. It can be understood that, if the values of frequency dividing numbers M and N can be variably set independent of each other in this manner, various frequencies can be obtained from one resonant frequency fc, as described below. For example, when the frequency dividing number M is 10, frequencies fp of 0.1 fc and 0.2 fc can be obtained. As frequencies between these two frequencies, four frequencies of fc/9, fc/8, fc/7, and fc/6 can be obtained by suitably changing the frequency dividing numbers M and N. Thus, frequencies of the multiplied signal output from the PLL circuit can be set with very fine pitches by using one quartz resonator. It is apparent that the pitches with which frequencies can be set can be made finer by increasing the frequency dividing number M for the reference divider RD. Conversely, even if a quartz resonator whose resonant frequency fc is different from the ideal resonant frequency is employed, a multiplied signal of a desired frequency can also be obtained by suitably setting the frequency dividing numbers M and N.
Thus, the oscillator of the present invention is characterized by comprising a piezoelectric resonator such as a quartz resonator, an oscillation signal output section for oscillating the piezoelectric resonator to output an oscillation signal of a first frequency, a first programmable divider (reference divider: RD) for dividing the frequency of the oscillation signal by a first frequency dividing number (frequency dividing number M) to obtain a reference signal of a second frequency, a PLL circuit section capable of operating by using the reference signal input thereto to obtain a multiplied signal of a third frequency, the multiplied signal being formed by multiplying the input signal by a second frequency dividing number (frequency dividing number N) for a second programmable divider (feedback divider: FD) provided
Ichinose Kazushige
Kano Toshihiko
Karasawa Hideo
Shigemori Mikio
Grimm Siegfried H.
Oliff & Berridg,e PLC
Seiko Epson Corporation
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