Oscillators – Ring oscillators
Reexamination Certificate
2000-02-18
2003-09-09
Kinkead, Arnold (Department: 2817)
Oscillators
Ring oscillators
C331S175000, C326S093000, C326S095000, C365S233100, C365S189110
Reexamination Certificate
active
06617935
ABSTRACT:
TECHNICAL FIELD
The present invention relates to an improved oscillator and more particularly to an oscillator having an improved current source such that the frequency of oscillation remains substantially constant at all voltages.
BACKGROUND OF THE INVENTION
Oscillators or timing devices are well known in the art. They are typically used with a charge pump to increase the voltage output of a charge pump for use in, e.g., non-volatile memory arrays. Thus, an oscillator in such an application must oscillate at a set frequency over a wide range of voltages.
In the prior art, as shown in
FIG. 1
, an oscillator
10
typically comprises two sections: a current source
12
and a plurality of odd numbered serially connected inverters
16
. The current source
12
comprises a number of current paths with each path having a plurality of serially connected resistors
30
a
(or
30
b
, or
30
c
) connected to an associated PMOS transistor
32
a
(or
32
b
, or
32
c
) which acts as a switch to turn on the current path. Thus, the transistor
32
a
is turned on when the chip erase operation is performed and current flows from Vdd through the PMOS transistor
32
a
through the serially connected resistors
30
a
. Similarly, if a sector erase signal is activated, PMOS transistor
32
b
is activated causing current to flow from Vdd through the serially connected chain of resistors
30
b
. The current path flowing through the different resistors
30
a
,
30
b
, or
30
c
all flow through node
40
.
The node
40
is connected to a plurality of odd numbered serially connected inverters
16
(
a-g
). Each inverter, e.g. inverter
16
a
, comprises an input, e.g.
42
a
as the input to the inverter
16
a
, and an output e.g.
44
a
which is the output to the inverter
16
a
. The plurality of odd numbered serially connected inverters
16
(
a-g
) are connected with an output of one inverter, e.g.
44
a
, connected to the input of an adjacent inverter, e.g.
42
b
. The output
44
g
of the last in the chain of serially connected inverters
16
(
a-g
) is connected to the input
42
a
of the first inverter
16
a.
Each inverter
16
further comprises a first PMOS transistor
18
having a source, a drain, and a gate for controlling the current flow between the source and drain all as well known in the art. In addition, each inverter comprises a first NMOS transistor
20
having a source, a drain, and a gate for controlling the flow of current therebetween. The gates of the first PMOS transistor
18
and the NMOS transistor
20
are connected together and to the input
42
. The source of the NMOS transistor
20
is connected to the source of the PMOS transistor
18
and to the output
44
of the inverter
16
. The drain of the PMOS transistor
18
is connected through a second PMOS transistor
48
and then to a source of voltage Vdd. The drain of the first NMOS transistor
20
is connected to the source of a second NMOS transistor
22
whose gate is connected to the node
40
. Finally, the drain of the second NMOS transistor
22
is connected to ground.
Thus, all of the gates of the second NMOS transistors
22
(
a-g
) are connected together and to the node
40
of the current source
12
.
In the operation of the oscillator
10
, once a signal, such as program, sector erase or chip erase is activated turning on PMOS transistor
32
a
, or
32
b
, or
32
c
, then current flows through the serially connected resistors
30
a
,
30
b
, or
30
c
to the node
40
. At that point, a voltage appears at node
40
which turns on the second NMOS transistors
22
(
a-g
). The odd number of serially connected inverters
16
(
a-g
) then begin inverting and oscillating. Since there are an odd number of inverters
16
, the inverters
16
will continually generate a stream of oscillating signals. The signals can then be outputted at node
60
. The output of the signals at node
60
is shown graphically in FIG.
2
.
As can be seen in
FIG. 2
, the period of oscillation for the oscillator
10
varies as a function of the voltage. In other words, the frequency of oscillation is slower at higher Vdd than at lower Vdd, where Vdd is the supply voltage of the circuit and is shown as the peak value of the waveforms in FIG.
2
.
Thus, one of the problems with the prior art oscillator
10
is that the frequency of oscillation varies as a function of the voltage.
SUMMARY OF THE INVENTION
In the present invention, a current source for an oscillator comprises a resistor and an MOS transistor having a first terminal and a second terminal with a channel therebetween and a gate for controlling the current flow therebetween. The first terminal and the second terminal of the MOS transistor are connected in parallel with the resistor. A voltage is connected to the gate of the MOS transistor to maintain the MOS transistor in a conduction state. By having the MOS transistor in a conduction state connected in parallel with the resistor of the current source, variations of the frequency of oscillation as a function of voltage is substantially decreased.
REFERENCES:
patent: 5359301 (1994-10-01), Candage
patent: 5544120 (1996-08-01), Kuwagata et al.
patent: 5896068 (1999-04-01), Moyal
Gray Cary Ware & Freidenrich LLP
Kinkead Arnold
Silicon Storage Technology, Inc.
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