Oscillation control circuit

Details Oscillation control circuit Oscillation control circuit

2001-11-29

2004-02-10

Pascal, Robert (Department: 2817)

Oscillators

Electromechanical resonator

Crystal

C331S074000, C331S10800D

Reexamination Certificate

active

06690245

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an oscillation control circuit.
2. Description of the Related Art
A conventional technique of an oscillation control circuit is known as disclosed, for example, in Japanese patent No. 2585147. This conventional technique is hereinafter described by referring to
FIGS. 9-11
.
FIG. 9
is an electrical circuit diagram showing one example of the conventional technique.
FIGS. 10A
,
10
B, and
10
C are a characteristic diagram showing the input/output characteristics (transfer characteristics) of CMOS inverters of FIG.
9
.
FIG. 11
is a time chart illustrating the operation of FIG.
9
.
A CMOS inverter IV
8
has input/output characteristics (transfer characteristics) as shown in FIG.
10
(A), and has its inversion potential (logical threshold voltage) set at 2.5 volts, for example. The inversion potential referred to herein is an input voltage midway between the fall start input voltage and the fall end input voltage of the input/output characteristics. Normally, it is an input voltage when the output voltage (2.5 V) is half the power-supply voltage (e.g., 5.0 V). A quartz oscillator QZ and a feedback resistor R
5
are connected in parallel between the input and output of the CMOS inverter IV
8
. The input and output terminals are grounded via capacitors C
5
and C
6
, respectively. The CMOS inverter IV
8
, quartz oscillator QZ, feedback resistor R
5
, and capacitors C
5
, C
6
together form an oscillator circuit.
A CMOS inverter IV
9
has input/output characteristics as shown in
FIG. 10B
, and has its inversion potential set at 2.0 volts, for example. The input terminal of the CMOS inverter IV
9
is connected with the output terminal of the CMOS inverter IV
8
, while the output terminal is connected with the gate of an N-channel MOS transistor T
56
. The source of the N-channel MOS transistor T
56
is grounded. The drain is connected with one end of a resistor R
6
, with one end of a capacitor C
7
, and with the input terminal of a CMOS inverter IV
10
. The other end of the resistor R
6
and the other end of the capacitor C
7
are connected with a power supply terminal VDD (5.0 volts). The resistor R
6
has a resistance value sufficiently larger than the ON-state resistance value of the MOS transistor T
56
. The CMOS inverters IV
9
, IV
10
, MOS transistor T
56
, resistor R
6
, and capacitor C
7
described thus far together form an operation control circuit OPC.
The gate of an N-channel MOS transistor T
51
is connected with the output terminal of the CMOS inverter IV
10
. The gate of a P-channel MOS transistor T
54
is connected with the output terminal of the CMOS inverter IV
10
via a CMOS inverter IV
11
. The junction of the gates of the N-channel MOS transistor T
52
and P-channel MOS transistor T
53
is connected with the output terminal of the CMOS inverter IV
8
. The junction of their drains is connected with a circuit LA at a later stage. The source of the N-channel MOS transistor T
52
is grounded via the source/drain of the N-channel MOS transistor T
51
. The source of the P-channel MOS transistor T
53
is connected with the power supply terminal VDD via the source/drain of the P-channel MOS transistor T
54
. The CMOS inverter IV
11
, N-channel MOS transistors T
51
, T
52
, and P-channel MOS transistors T
53
, T
54
described thus far together form a CMOS clocked inverter. The circuit LA at the later stage is connected with the output of this CMOS clocked inverter.
When the logical output value of the CMOS inverter IV
10
is 0, the P-channel MOS transistor T
55
shorts out the output from the CMOS inverter formed by the MOS transistors T
52
and T
53
.
The operation of the electric circuit of
FIG. 9
is described by referring to
FIG. 11. A
, B, C, D, and E of
FIG. 11
correspond to points a, b, c, d, and e, respectively, of FIG.
9
.
As shown in
FIG. 11A
, when the power supply is turned on, the CMOS inverter IV
8
produces an oscillation signal of minute amplitude. Although the amplitude of this oscillation signal increases gradually, the logical output value of the CMOS inverter IV
9
is kept at 0 (
FIG. 11B
) until the oscillation potential drops below the inversion potential (2.0 V) of the CMOS inverter IV
9
. Therefore, the MOS transistor T
56
is driven off. The output of the CMOS inverter IV
10
assumes a logical value of 0 (FIG.
11
D). As a result, the MOS transistors T
51
and T
54
are cut off. The CMOS inverter formed by the MOS transistors T
52
and T
53
is deactivated. At this time, the MOS transistor T
55
is ON and so the output from the CMOS inverter formed by the MOS transistors T
52
and T
53
is shorted out via the MOS transistor T
55
. In this way, the CMOS inverter formed by the MOS transistors T
52
and T
53
is maintained in inoperative state until the oscillation potential of the oscillation signal exceeds the inversion potential (2.0 V) of the CMOS inverter IV
9
. Its logical output value is kept at 1.
When the oscillation potential of the oscillation signal exceeds the inversion potential (2.0 volts) of the CMOS inverter IV
9
, the output from the CMOS inverter IV
9
assumes a logical value of 1 (FIG.
11
B), turning on the MOS transistor T
56
. As a result, as shown in
FIG. 11C
, the capacitor C
7
is charged through the MOS transistor T
56
. The input voltage to the CMOS inverter IV
10
drops rapidly. When the MOS transistor T
56
is cut off, electric charge in the capacitor C
7
is released via the resistor R
6
. The input voltage to the CMOS inverter IV
10
rises mildly. When the input voltage to the CMOS inverter IV
10
drops below its inversion potential, the logical output value of the CMOS inverter IV
10
is inverted from 0 to 1. As a result, the CMOS inverter formed by the MOS transistors T
52
and T
53
is first set into operation. At the same time, the MOS transistor T
55
is turned off. By setting the resistance value of the resistor R
6
sufficiently greater than the ON-state resistance value of the MOS transistor T
56
, the logical output value of the CMOS inverter IV
10
remains at 1, as shown in FIG.
11
D. The oscillation signal generated by the CMOS inverter IV
8
is inverted by the CMOS inverter formed by the MOS transistors T
52
and T
53
. As shown in
FIG. 11E
, a clock signal having a duty cycle of 50% can be produced. This inverted output (clock signal) sets the circuit LA at the later stage into operation.
The circuit at the later stage is set into operation after the amplitude of the oscillation signal reaches a certain magnitude in this way. Consequently, the problem that the oscillation operation is made unstable by the effect of noise produced by the circuit at the later stage to thereby hinder shift from the oscillating operation with minute amplitudes to steady-state amplitude oscillating operation can be solved.
However, it has been required that the oscillator circuit use a higher frequency and consume a less amount of electric power. Therefore, smaller-sized quartz oscillators and lower power-supply voltages have been adopted. With this trend, there is a demand for a decrease in the steady-state amplitude of the oscillation signal.
FIG. 12
is a time chart illustrating the operation of the electric circuit of
FIG. 9
where the steady-state amplitude of the oscillation signal is suppressed in the conventional case described above. Note that A, B, C, D and E of
FIG. 12
correspond to points a, b, c, d, and e, respectively, of FIG.
9
.
Since the steady-state amplitude of the oscillation signal is small, the time for which the oscillation potential of the oscillation signal is in excess of the inversion potential (2.0 V) of the CMOS inverter IV
9
is shortened as shown in FIG.
12
A. Therefore, the time for which the output from the CMOS inverter IV
9
assumes a logical value of 1 is shortened and the time for which the output assumes a logical value of 0 is prolonged as shown in FIG.
12
B. Consequently, the input voltage to the CMOS inverter IV
10
drops rapidly in a shorter time and rises mildly in a longer ti

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