Orthogonal code generating circuit

Details Orthogonal code generating circuit Orthogonal code generating circuit

2006-04-18

2006-04-18

Vanderpuye, Kenneth (Department: 2638)

Pulse or digital communications

Spread spectrum

Direct sequence

C708S410000

Reexamination Certificate

active

07031369

ABSTRACT:
An orthogonal code generating circuit10is arranged by a counter circuit unit12, a combination circuit unit14of orthogonal codes, and a control circuit unit16. Furthermore, the combination circuit unit14is constructed of an AND gate14aand an exclusive-OR gate14b. The control circuit unit16outputs a decode output in response to a set code designation signal CNo. When a code generation starting signal ST is inputted, a counter circuit12starts to output a counter output. Both the decode output and the counter output are entered to the combination circuit unit14which AND-gates the corresponding output bits with each other, and thereafter, exclusively OR-gates the AND-gated outputs, and then outputs the exclusively OR-gated signal as serial data of an orthogonal code. As a consequence, since the conventional ROM unit for storing thereinto the orthogonal codes can be omitted, the circuit scale of the orthogonal code generating circuit10can be reduced.

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patent: 6181732 (2001-01-01), Komatsu
patent: 6515980 (2003-02-01), Bottomley
patent: 11-177529 (1999-07-01), None
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patent: WO 95/03652 (1995-02-01), None
patent: WO 01/50658 (2001-07-01), None

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