Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices
Reexamination Certificate
1999-12-17
2002-04-16
Sircus, Brian (Department: 2839)
Electricity: electrical systems and devices
Housing or mounting assemblies with diverse electrical...
For electronic systems and devices
Reexamination Certificate
active
06373715
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to signal routing. More particularly, the present invention relates to a topology for mounting processors on two sides of a printed circuit board (PCB).
BACKGROUND OF THE INVENTION
Processors, such as micro-processors found in a digital computer, read and write data using electronic signals. As the speed of processors continues to increase, along with the amount of data processed, the successful transfer of the electronic signals becomes more difficult. Given the clear trend towards faster and more complex processors in modem computer systems, improved techniques for transferring signals are needed in order to keep pace.
An “idealized digital electronic signal”
10
is shown in FIG.
1
. Signal
10
may transition between a low voltage level
12
and high voltage level
14
over a period of time. Of course, not all signals
10
switch between high voltage
14
and low voltage
12
states each cycle, although, some may. These voltage levels typically correspond to a digital zero or one for time periods t
2
to t
3
and t
4
to t
5
, respectively. The transition time between low voltage
12
and high voltage
14
is depicted as time period t
1
to t
2
. The rate of transition between voltages
12
and
14
is referred to as the “edge rate”. Preferably, the transitions from voltages
12
to
14
and from
14
to
12
are symmetrical. Electronic devices typically need some amount of time to read, or latch onto, a given voltage. That is, time periods t
2
to t
3
and t
4
to t
5
of signal
10
may have preferred minimum durations at voltages
12
and
14
, dependent on the particular electronic devices used in a circuit and the sampling time needed by the devices. For a given edge rate and preferred minimum durations, a maximum frequency for signal
10
can be defined. Beyond this maximum frequency, devices may fail to correctly read signal
10
. Alternatively, increasing the edge rate of a signal
10
, at a given frequency would increase the duration at voltages
12
and
14
. However, a faster edge rates may increase noise, that may also complicate reading the intended signal value. Discontinuities in the signal path also tend to increase the noise.
As will be further explained below, the maximum edge rate for a given design is correlated to the length of the conductors connected to the processor. That is, fast signal transition times work best with short conductors. Also, short conductors permit signals to travel their entire lengths faster than longer conductors. However, the design of a system is typically based on a worst case situation where all possible signal
10
transitions must be considered. Thus, the general design guideline is to keep signal paths short for the best signal transmission performance.
There are many possible topologies, or signal routing paths between the components of a computer system. As a general rule-of-thumb, designers try to keep signal paths short. However, there are many possible topologies and design choices. It would be advantageous to define topologies, or design guidelines for achieving such topologies, so that adequate signal transmission performance for the entire system is accomplished in systematic way. Current trial and error layout methods are cumbersome and, as system complexity increases, are more difficult for designers work with using rule-of-thumb such as keeping signal paths short.
Many computer system applications call for multiple processors working together. The system architecture for such multiple processor systems can take many forms. For example, using separate printed circuit boards (PCBS) for connecting individual processors to the overall system is known in the art. However, the transfer of signals
10
among separate PCBs takes time, and this may be a constraint on systems using relatively fast processors. Combining multiple processors on a single PCB is one approach to keeping the signal paths short. There are, however, many possible ways of mounting the multiple processors on a single PCB, and routing signals
10
among them.
The present invention considers factors including the lengths of signal paths, both within the processors and on the PCB, the relative orientation of the conductors, and the relative orientation of similar processors in order to achieve an improved quality of signal
10
transmissions. A signal path may be divided into two elements, as will be further described below, a stub and an offset. An embodiment of the present invention matches long stub lengths with long offset length, and short stub lengths with short offset lengths in order to define a topology that improve the signal transmission characteristics. Such a topology has the additional benefit of simplifying the layout of signal paths for a system with multiple processors.
SUMMARY OF THE INVENTION
A topology for mounting processors on opposite sides of a printed circuit board (PCB) orients rows of processor connection pins parallel to the bus orientation within the PCB and defines a relative 180 degree orientation between the opposing processors.
REFERENCES:
patent: 5212494 (1993-05-01), Hofer et al.
patent: 5999437 (1999-12-01), Chengson et al.
Dabral Sanjay
Zeng Ming
Kenyon & Kenyon
Prasad Chandrika
Sircus Brian
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