Organization for an integrated circuit calculator/controller

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2353034, G06F 916

Patent

active

041551184

ABSTRACT:
An organization for a single chip calculator/controller which reduces the number of interconnections necessary in an integrated circuit chip. The single chip calculator/controller comprises an arithmetic logic unit (ALU) and a plurality of active storage elements all interconnected in parallel via an input bus and an output bus. Instructions contained in a read only memory (ROM) are read out into an instruction register. A first means is provided for decoding a portion of the instruction to generate a configuration signal for selectively configuring the logic elements of the ALU. A second means is provided for decoding the remainder of the instruction to generate a register select signal for selectively actuating a chosen storage element. The calculator/controller system also includes data clocking and input/output means. The centralization of the logic functions in the ALU allows any instruction to act upon the data contents of any active storage element.

REFERENCES:
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patent: 3544973 (1970-12-01), Borck et al.
patent: 3955180 (1976-05-01), Hirtle
patent: 3997895 (1976-12-01), Cassonnet et al.
patent: 4014005 (1977-03-01), Fox et al.
patent: 4028682 (1977-06-01), Weber
patent: 4050058 (1977-09-01), Garlic

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