Organic substrate for flip chip bonding

Details Organic substrate for flip chip bonding Organic substrate for flip chip bonding

2002-05-07

2004-07-27

Loke, Steven (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S773000, C257S778000, C257S786000

Reexamination Certificate

active

06768206

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor packaging, and in particular, to an organic substrate for flip chip semiconductor packages.
BACKGROUND OF THE INVENTION
Referring to
FIGS. 1 and 2
, a flip chip bonding configuration for a semiconductor package
10
that includes a semiconductor die
12
that is mechanically and electrically connected to a supporting substrate
14
. Metallic bumps
16
on the bottom surface
18
of the die
12
overlap with metallic pads
20
correspondingly positioned in a die bonding region
22
located on the top surface
24
of the substrate
14
. Typically, the metallic bumps
16
are connected to the underlying pads
20
by solder
26
, thus providing direct electrical coupling between the die
12
and substrate
14
. The direct electrical interconnection between the die
12
and substrate
14
provided by flip chip bonding configuration
10
advantageously eliminates the need for bond wires and results in low resistance and inductance values. Thus, flip chip bonding configurations provide for better signal integrity and power distribution to and from the die
12
than in other bonding technologies such as wire bonding or tape automated bonding.
The bottom surface
18
of the die
12
may include hundreds of metallic bumps
16
with each metallic bump providing an electrical interface to and from the die
12
for various electrical signals, core power, input/output (I/O) power, and ground. Electrical signals, core power, and ground are provided to the die's internal logic circuitry (not shown). Similarly, the I/O power and ground are provided to the die's I/O interface circuitry (not shown), i.e., input and output drivers. The metallic bumps
16
, and therefore the corresponding pads
20
on the top surface
24
of the substrate
14
, generally are arranged in concentric rectangular rings (not shown) and are spaced apart to prevent electrical shorting between adjacent metallic bumps/pads. However, the metallic bumps
16
and pads
20
may be configured in various patterns other than concentric rectangular rings.
The substrate
14
may be a multi-layer printed circuit board, ceramic substrate or another semiconductor chip. Typically, pads
28
on the bottom surface
30
of the substrate
14
are bonded, e.g., via solder
32
, to another printed circuit board referred to as a motherboard
34
. The substrate
14
provides for a mechanical and electrical interface between the often densely-packed metallic bumps
16
on the bottom surface
18
of the die
12
to less-densely packed pads (not shown) on the motherboard
34
. The pads
28
on the substrate's bottom surface
30
are placed so as to correspond to the pads (not shown) on the motherboard
34
.
The various layers of the substrate
14
are formed by the well known processes used to create integrated circuits and printed circuit boards. The individual layers may be comprised of conductive or semiconductor material. Often, the conductive material is a metal, i.e., a copper-based material, which is plated onto semiconductor material layers and patterned by photolithographically removing deposited metal to form pads and traces. The substrate
14
may be referred to as organic if organic material is combined with the copper-based material so as to provide thermal expansion characteristics close to those of the motherboard
34
and to improve reliability in board assembly.
Traces (not shown) electrically interconnect pads
20
or
28
on either the top surface
24
or bottom surface
30
of the substrate
14
or to vias (not shown) which are holes that facilitate the electrical interconnection of the various layers of the substrate
14
. The vias may be formed, for example, by mechanical or laser drilling a via hole through a layer or layers of the substrate
14
. Surrounding the via hole on each level may be a circular land (not shown) made of a conductive material. Typically, the via hole is filled with a conductive material so that via lands surrounding the via holes on various layers of the substrate are electrically interconnected. A via may extend through to the bottom surface
30
of the substrate
14
and connect to a pad
28
. Thus, the pads
20
and
28
on the top surface
24
and bottom surface
30
, respectively, of the substrate
14
are interconnected to one another by means of traces and vias. Solder balls
32
are individually connected to each pad
28
for soldering the pads
28
on the bottom surface
30
of the substrate
14
to the corresponding pads (not shown) on the motherboard
34
. The solder balls
32
connected to the pads
28
on the bottom surface
30
of the substrate
14
are collectively called a ball grid array
36
.
Various electrical characteristics are considered when designing the substrate
14
including maintaining a low DC resistance and AC inductance for power and ground connections to and from the die
12
, and maintaining wide spacing between traces (not shown), pads
20
and
28
, and via lands (not shown) to minimize the possibility of crosstalk or electrical shorting. Thus, with respect to power distribution for the die
12
, the distance between the pads
20
on the top surface
24
of the substrate
14
for core power distribution and the logic circuitry which actually consume the power should be as short as possible.
Recently, many semiconductor packages have been designed using C4 flip chip bonding technology. An exemplary C4 bonding technology pad arrangement
38
is shown in the top plan view of FIG.
3
. Referring additionally to
FIGS. 1 and 2
, the C4 bonding technology utilizes pads
40
arranged in an area array in the die bonding region
22
on the top surface
24
of the substrate
14
that are separated from one another by a pitch “p”. In
FIG. 3
, the pads
40
are positioned at lattice points
41
(only numbered along one row and one column), where each lattice point
41
is located below the midpoint of each pad
40
.
In
FIG. 3
, the top two rows
42
and
44
of pads
40
from adjacent the die edge are rows of signal pads
46
that accommodate the transfer of various electrical signals to and from the die
12
. The top two rows
42
and
44
of pads
40
closest to the die edge
48
include signal pads
46
because the majority of the logic circuitry within the die
12
is located proximate to the die edge
48
and signal traces (not shown) on the top surface
24
of the substrate
14
are typically routed outside of the die bonding region
22
. The third and fourth rows
50
and
52
, respectively, of pads
40
down from the die edge
48
include core power pads
54
, for the transfer of power to the logic circuitry in the die
12
, I/O power pads
56
, for the transfer of power to the I/O interfaces in the die
12
, and ground pads
58
, for providing ground connections to the die. The fifth and sixth rows
60
and
62
, respectively, of pads
40
down from the die edge
48
are again rows of signal pads
46
. The seventh and eighth rows
64
and
66
, respectively, of pads
40
are core power pads
54
and ground pads
58
. Thus, power and ground pads
54
and
58
, respectively, are intermingled with the signal pads
46
so as to avoid problems that occur when large numbers of signal pads
46
result in the power and ground pads
54
and
58
, respectively, being located further than three to four rows away from the die edge. The three dots
68
in the upper left hand corner, upper right hand corner, and the bottom of
FIG. 3
indicate that the number and spacing between the pads
40
included in the pad arrangement
38
can vary along the top surface
24
of the substrate
14
in those directions.
FIG. 3
indicates examples of the maximum distances between the die edge
48
, where the logic circuitry is assumed to be located, and a core power pad
54
and an I/O power pad
56
. A maximum distance between the die edge and a core power pad is approximately 3.354 p (3.354 times p), where p is the pitch or distance between the midpoints of adjacent pads
40
. Also, a maximum distance betwe

Affiliated with

Also associated with

Rating

Organic substrate for flip chip bonding does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Organic substrate for flip chip bonding, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Organic substrate for flip chip bonding will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3231583