Organic sidewall spacers used with resist

Details Organic sidewall spacers used with resist Organic sidewall spacers used with resist

1999-03-18

2001-05-08

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S424000, C438S438000, C257S394000

Reexamination Certificate

active

06228747

ABSTRACT:

BACKGROUND AND SUMMARY OF THE INVENTION
The present invention relates to integrated circuit structures and fabrication methods.
BACKGROUND: SCALING
A continuing trend in integrated circuit device technology, for a great many years, has been the steady shrinkage of device dimensions. This shrinkage has preceded on a fairly steady exponential curve for many years. The minimum patterned dimension is commonly referred to as the “critical dimension.” With conventional MOS technology, as the critical dimension shrinks, the gate oxide becomes thinner, the diffusions become shallower, and the transistor minimum channel length becomes smaller. Commonly the supply voltage is also reduced. Further details regarding conventional scaling strategies can be found, for example, in Voorde, “MOSFET scaling into the future,” Hewlett-Packard Journal, vol. 48, no. 4, pp. 96-100 (Aug. 1997), which is hereby incorporated by reference.
BACKGROUND: SHALLOW TRENCH ISOLATION
A very popular isolation method in current semiconductor processing is shallow trench isolation. One persistent problem which has been encountered is the edge effect at the top corners of the trenches. If the oxide at the edges of the trenches is too thin, or if the boundary between the oxide and silicon forms too sharp a corner, the electrical field may create inversion so that a parasitic transistor exists. This is especially a problem in circuits which operate with dual voltages and in embedded flash processes, since transistors can have different thicknesses of gate oxides. In these processes, an extra HF etch can thin the oxide at the STI corner. Many solutions to this problem are currently under study, as exemplified by the following articles, all of which are hereby incorporated by reference: Iwamoto et al., H
IGHLY
-R
ELIABLE
U
LTRA
T
HIN
G
ATE
O
XIDE
F
ORMATION
P
ROCESS
, 1996 IEDM, p. 29.7.1-29.7.4; Kim et al., N
ITRIDE
C
LADDED
P
OLY
-S
I
S
PACER
L
ocos
(NCPSL) I
SOLATION
T
ECHNOLOGY
F
OR
T
HE
1 G
IGA
B
IT
D
RAM
, 1996 IEDM, p. 32.2.1-32.2.4; Chatterjee et al., A S
HALLOW
T
RENCH
I
SOLATION USING
LOCOS E
DGE FOR
P
REVENTING
C
ORNER
E
FFECTS FOR
0.25/0.18 M
ICRON
CMOS T
ECHNOLOGIES AND
B
EYOND
, 1996 IEDM, p. 32.3.1-32.3.4; Watanabe et al., C
ORNER
-R
OUNDED
S
HALLOW
T
RENCH
I
SOLATION
T
ECHNOLOGY TO
R
EDUCE THE
S
TRESS
-I
NDUCED
T
UNNEL
O
XIDE
L
EAKAGE
C
URRENT FOR
H
IGHLY
R
ELIABLE
F
LASH
M
EMORIES
, 1996 IEDM, p. 32.4.1-32.4.4; Chen et al., A N
OVEL
0.25 M
ICRON
S
HALLOW
T
RENCH
I
SOLATION
T
ECHNOLOGY
, 1996 IEDM, p. 32.5.1-32.5.4; Chang et al., A H
IGHLY
M
ANUFACTURABLE
C
ORNER
R
OUNDING
S
OLUTION FOR
0.18 M
ICRON
S
HALLOW
T
RENCH
I
SOLATION
, 1997 IEDM, p. 27.2.1-27.2.4; Shum et al., C
ORNER
F
IELD
E
FFECT OF THE
CMP O
XIDE
R
ECESS IN
S
HALLOW
T
RENCH
I
SOLATION
T
ECHNOLOGY FOR
H
IGH
D
ENSITY
F
LASH
M
EMORIES
, 1997 IEDM, p. 27.3.1-27.3.4.
BACKGROUND: FORMATION OF CONTACTS
As the size of contact and via holes shrink, it has been necessary to use thinner photo-resist. This, in turn, means that a less aggressive oxide etch must be used, so that the photo-resist is not destroyed in the process. Additionally, when using thinner resist, the contact or via etch must have greater selectivity to resist, and this requirement is approaching the limitation of current etches.
BACKGROUND: LINE/SPACE ADJUSTMENT
As the limits of current lithographic techniques are reached, methods of attaining smaller sized structures have been explored. It is known to use sidewall spacers on masking structures as a means to attain sub-lithographic dimensions. I.e., as seen in
FIG. 4A
, sidewall spacers
412
are added to masking layer
410
to decrease the opening
414
below the limits of the lithography. Masking layer
410
can be a hard mask, such as silicon nitride, or it can be a structural feature, such as a gate line; the spacers are typically an oxide, nitride, or other suitable material. However, this technique has been limited by the fact that the available materials for forming sidewalls require high temperature processing, and their use is thus incompatible with the presence of photo-resist.
Organic Sidewall Spacers
It is herein disclosed to use organic materials, such as parylene and plasma deposited polymers, for disposable spacers. One class of embodiments uses disposable organic spacers in combination with definition of a shallow-trench-isolation pattern, to promote rounding of the trench edge and protection of this edge during subsequent etches. Another class of embodiments uses disposable organic spacers to decrease the size of contact holes and vias. Since the lithographic size of the hole in the photo-resist can be increased for a given end result, this allows a thicker photo-resist to be used, with the consequent ability to use a more aggressive oxide etch, while decreasing etch selectivity limits. Another class of embodiments uses disposable organic sidewall spacers in combination with photo-resist to permit alteration of the line-to-space ratio, and to create sub-lithographic structures.
A particular advantage of the use of organic materials as spacers is that they can be removed by ashing, which is not only a fairly benign process, but also one which must already be performed to remove photo-resist after patterning steps. Thus, the disclosed inventions provide new degrees of freedom for pattern adjustment while imposing minimal additional process complexity.
The disclosed methods and structures have the following advantages, although not every embodiment shares all the advantages:
can be used in combination with resist;
spacers can be ashed along with resist;
use in STI promotes rounding of corner of trench;
use in STI allows more coverage of corners with fill oxide;
eliminates leakage at corners of STI trench;
lithographic requirements can be relaxed for a given feature size, or alternatively, sub-lithographic features can be created;
less expensive stepper can be used;
allows use of thicker resist;
allows use of less selective etch;
wider process margin for patterning.


REFERENCES:
patent: 4889827 (1989-12-01), Willer
patent: 5365097 (1994-11-01), Kenney
patent: 5422294 (1995-06-01), Noble, Jr.
patent: 5512767 (1996-04-01), Noble, Jr.
patent: 5641694 (1997-06-01), Kenney
patent: 5744386 (1998-04-01), Kenney
patent: 5798553 (1998-08-01), Furukawa et al.
patent: 5945724 (1999-08-01), Parekh et al.
patent: 6008108 (1999-12-01), Huang et al.

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