Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2000-01-13
2001-05-08
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S690000, C257S700000, C257S702000, C257S772000, C257S781000, C257S779000
Reexamination Certificate
active
06229207
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an organic carrier member for mounting a semiconductor device, and more particularly to an organic carrier member having pin leads mounted thereon.
2. Background Art
The escalating requirements for high density and performance associated with ultra-large scale integration technology creates significant challenges for the design and implementation of electrical connections between circuit components and external electrical circuitly.
Integrated circuit (IC) devices whether individual active devices, individual passive devices, multiple active devices within a single chip, or multiple passive and active devices within a single chip, require suitable input/output (I/O) connections between themselves and other circuit elements or structures. These devices are typically very small and fragile. Because of their size and fragility, they are commonly carried on substrates for support, i.e., carrier members.
Device miniaturization and the ever increasing density of semiconductor devices require an ever increasing number of I/O terminals, shorter connections and improvements in the electrical connections, heat dissipation and insulation characteristics of the carrier member. This problem is exacerbated in manufacturing semiconductor devices having a design rule of about 0.18 microns and under.
One technique that supports the increased device densities is the shift from peripheral wire bonding to area array chip interconnects. Area array chip interconnects use bumps or solder joints that directly couples the IC chip or die to the carrier member. This technique accommodates an increased number of I/O terminals and provides electrical signals immediately below the chip, improving voltage noise margins and signal speed. One type of area array interconnect packaging technique is the flip chip (FC) solder interconnect on a carrier member.
In the flip chip assembly or package, the IC die and other devices are “bumped” with solder bumps or balls, i.e. a plurality of discrete solder bumps are formed over metal contacts on the surface of the die. The chip is then turned upside down or “flipped” so that the device side or face of the IC die couples to the carrier member such as found in a ceramic or plastic carrier member having balls, pins or land grid arrays. The solder bumps of the device are then attached to the carrier member forming an electrical and mechanical connection.
The carrier member conventionally employs a multi-layer substrate constructed of a plurality of laminated dielectric and conductive layers where individual IC chips are mounted to the top layer of the substrate. A pre-defined metallization pattern lies on each dielectric layer within the substrate. Metallization patterns on certain layers act as voltage reference planes and also provide power to the individual chips. Metallization patterns on other layers route signals between individual chips. Electrical connections to individual terminals of each chip and/or between separate layers are made through well-known vertical interconnects called “vias”. Interconnect pins are bonded to metallic pads situated on the face of the substrate and are thereby connected to appropriate metallization patterns existing within the substrate. These interconnect pins route electrical signals between a multi-chip integrated circuit package and external devices.
As illustrated in
FIG. 1
, a conventional flip chip assembly
8
includes a device or IC die
10
mechanically and electrically attached to substrate
16
by a plurality of solder bumps
12
connected to solder pads
14
on substrate
16
. Solder pads
14
are electrically connected to I/O pin leads
18
by internal wiring (not shown for illustrative convenience) throughout substrate
16
. Pin leads
18
are used to provide the electrical connections to external circuitry. The assembly, thus, provides an electrical signal path from IC die
10
through solder/pad connections
12
/
14
through substrate
16
, by way of internal wiring, to an external circuitry by way of pin leads
18
.
As shown, substrate
16
has a plurality of solder pads
14
, which are generally formed by screen printing a coating of solder on the substrate. Solder bumps
12
on die
10
are generally formed by known solder bumping techniques and are conventionally formed of a high lead (Pb) solder, such as solders having from 97-95 wt % Pb and from 3-5 wt % of tin (Sn), which have a melting temperature of approximately 323° C. Substrate
16
can be made of ceramic or plastic materials. When the substrate is made of a ceramic, the electrical and mechanical interconnect between the die and substrate is conventionally achieved by reflowing the solder pads
14
and solder bumps
12
at a relatively high temperature, such as 350° C. to 370° C., to join solder bumps
12
and pads
14
between the die and substrate
16
. It is preferable to have the high melting interconnection on the die to avoid degradation of the die/substrate interconnection in subsequent thermal processing steps.
A known technique of mounting pin leads to a substrate involves coating metallized pads that serves as landing sites for the pins with an appropriate brazing or soldering alloy. The pins are then positioned over the coated metallized pads and the solder reflowed to join the pins to the pads.
One problem associated with attaching pin leads to metallized pads on a plastic or organic substrate is that the soldering temperature cannot be higher than the decomposition temperature of the substrate, without adversely compromising the mechanical integrity of the organic substrate. Further, the solders employed for joining pin leads to the substrate should form strong mechanical bonds capable of withstanding pulling, placement, or testing, i.e. socketing, the assembled carrier with good electrical signal. As the need for I/O leads increases and the need for lighter and smaller packages increase, the problems associated with packaging IC dies and capacitors creates new challenges.
Accordingly, a continuing need exists in the art for improved pin grid array packages permitting a strong, reliable, minimally resistive brazed joint formed between pin leads and metallized pads on an organic substrate.
SUMMARY OF THE INVENTION
An advantage of the present invention is an organic carrier member suitable for mounting a device with highly reliable pin leads.
Another advantage of the present invention is a device assembly that maintains reliable electrical connections during its operation.
Additional advantages and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The advantages of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a carrier member for mounting a device, such as an integrated circuit die, capacitor, etc. TIle carrier member comprises: an organic substrate having a plurality of conductive contacts thereon for receiving a device to be mounted thereto; a plurality of pads on the organic substrate which are in electrical communication with the conductive contacts on the organic substrate; and a plurality of pins mechanically and electrically joined to the pads by a solder fillet.
Advantageously, the solder fillet, joining the pads and pin leads, comprises a low weight percent (wt %) of tin and has a reflow temperature of less than about the decomposition temperature of the organic substrate and provides a high bond strength.
The organic substrate can comprise polyphenylene sulphide, polysulphone, polyethersulphone, polyarysulphone, phenol, polyamide, bismaleimide-triazine, epoxy or mixtures thereof with optionally fiberous materials, such as glass fibers, to fabricate a laminated structure with internal wiring connecting the solder p
Advanced Micro Devices , Inc.
Parekh Nitin
Thomas Tom
LandOfFree
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